Datasheet > CY7C1041CV33_10

CY7C1041CV33_10

更新时间： 2024-02-14 17:04:04

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	449K
描述
4-Mbit (256 K × 16) Static RAM

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中文翻译

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数据手册

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CY7C1041CV33_10 数据手册

CY7C1041CV33

4-Mbit (256 K × 16) Static RAM

4-Mbit (256

K × 16) Static RAM

Features

Functional Description

■ Temperature ranges

❐ Commercial: 0 °C to 70°C

The CY7C1041CV33 is a high performance CMOS static RAM

organized as 262,144 words by 16 bits.

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (/IO₀through I/O₇), is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

■ Pin and function compatible with CY7C1041BV33

■ High speed

❐ t_AA= 8 ns

Enable (BHE) is LOW, then data from IO pins (I/O₈through I/O₁₅

)

■ Low active power

❐ 360 mW (max)

is written into the location specified on the address pins (A₀

through A₁₇).

■ 2.0 V data retention

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. For more information, see the Truth

Table on page 10 for a complete description of Read and Write

modes.

■ Automatic power down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE and OE features

■ Available in Pb-free 44-pin TSOP II package

The input and output pins (I/O₀through I/O₁₅) are placed in a

high impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or during a write operation (CE LOW

and WE LOW).

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

INPUT BUFFER

256K x 16

RAM Array

I/O –I/O

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05134 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 4, 2011

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与CY7C1041CV33_10相关器件

型号	品牌	获取价格	描述	数据表
CY7C1041CV33-10BAC	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 10ns, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY7C1041CV33-10BAC	CYPRESS	获取价格	256K x 16 Static RAM
CY7C1041CV33-10BACT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY7C1041CV33-10BAI	CYPRESS	获取价格	256K x 16 Static RAM
CY7C1041CV33-10BAI	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 10ns, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY7C1041CV33-10BAIT	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 10ns, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY7C1041CV33-10BAXA	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041CV33-10BAXC	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041CV33-10BAXC	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 10ns, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48
CY7C1041CV33-10BAXCT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-4

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