Datasheet > CY7C1041CV33-10BAXCT

CY7C1041CV33-10BAXCT

更新时间： 2023-02-26 15:13:38

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
14页	427K
描述
Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48

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CY7C1041CV33

4-Mbit (256K x 16) Static RAM

Features

Functional Description

■ Temperature ranges

The CY7C1041CV33 is a high performance CMOS static RAM

organized as 262,144 words by 16 bits.

❐ Commercial: 0°C to 70°C

❐ Industrial: –40°C to 85°C

❐ Automotive-A: –40°C to 85°C

❐ Automotive-E: –40°C to 125°C

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇), is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

■ Pin and function compatible with CY7C1041BV33

Enable (BHE) is LOW, then data from IO pins (IO₈through IO₁₅

)

is written into the location specified on the address pins (A₀

through A₁₇).

■ High speed

❐ t_AA= 10 ns (Commercial, Industrial and Automotive-A)

❐ t_AA= 12 ns (Automotive-E)

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. For more information, see the Truth

Table on page 9 for a complete description of Read and Write

modes.

■ Low active power

❐ 324 mW (max)

■ 2.0V data retention

■ Automatic power down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE and OE features

The input and output pins (IO₀through IO₁₅) are placed in a high

impedance state when the device is deselected (CE HIGH), the

outputs are disabled (OE HIGH), the BHE and BLE are disabled

(BHE, BLE HIGH), or during a write operation (CE LOW and WE

LOW).

■ AvailableinPb-freeandnonPb-free44-pin400MilSOJ, 44-pin

TSOP II and 48-Ball FBGA packages

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

INPUT BUFFER

256K x 16

RAM Array

IO –IO

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05134 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 14, 2008

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与CY7C1041CV33-10BAXCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1041CV33-10BAXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041CV33-10BAXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-4
CY7C1041CV33-10VC	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 10ns, PDSO44, 0.400 INCH, SOJ-44
CY7C1041CV33-10VC	CYPRESS	获取价格	256K x 16 Static RAM
CY7C1041CV33-10VI	CYPRESS	获取价格	256K x 16 Static RAM
CY7C1041CV33-10VXC	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041CV33-10ZC	CYPRESS	获取价格	256K x 16 Static RAM
CY7C1041CV33-10ZC	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 10ns, PDSO44, TSOP2-44
CY7C1041CV33-10ZCT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, TSOP2-44
CY7C1041CV33-10ZI	CYPRESS	获取价格	256K x 16 Static RAM

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