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CY7C09369V-12AXC PDF预览

CY7C09369V-12AXC

更新时间： 2024-01-05 21:33:57
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 760K
描述
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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CY7C09369V-12AXC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.52最长访问时间：12 ns
最大时钟频率 (fCLK)：50 MHzI/O 类型：COMMON
JESD-30 代码：S-PQFP-G100JESD-609代码：e0
内存密度：294912 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：18功能数量：1
端口数量：2端子数量：100
字数：16384 words字数代码：16000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：16KX18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63SQ,20封装形状：SQUARE
封装形式：FLATPACK并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified最大待机电流：0.0001 A
最小待机电流：3 V子类别：SRAMs
最大压摆率：0.25 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

CY7C09369V-12AXC 数据手册

 浏览型号CY7C09369V-12AXC的Datasheet PDF文件第1页浏览型号CY7C09369V-12AXC的Datasheet PDF文件第3页浏览型号CY7C09369V-12AXC的Datasheet PDF文件第4页浏览型号CY7C09369V-12AXC的Datasheet PDF文件第5页浏览型号CY7C09369V-12AXC的Datasheet PDF文件第6页浏览型号CY7C09369V-12AXC的Datasheet PDF文件第7页 
CY7C09269V/79V/89V  
CY7C09369V/79V/89V  
A HIGH on CE0 or LOW on CE1 for one clock cycle will power  
down the internal circuitry to reduce the static power  
consumption. The use of multiple Chip Enables allows easier  
banking of multiple chips for depth expansion configurations.  
In the pipelined mode, one cycle is required with CE0 LOW and  
CE1 HIGH to reactivate the outputs.  
Functional Description  
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are  
high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x  
16/18 dual-port static RAMs. Two ports are provided,  
permitting independent, simultaneous access for reads and  
writes to any location in memory.[6] Registers on control,  
address, and data lines allow for minimal set-up and hold  
times. In pipelined output mode, data is registered for  
decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1, 2]  
(pipelined). Flow-through mode can also be used to bypass  
the pipelined output register to eliminate access latency. In  
flow-through mode data will be available tCD1 = 18 ns after the  
address is clocked into the device. Pipelined output or  
flow-through mode is selected via the FT/Pipe pin.  
Counter enable inputs are provided to stall the operation of the  
address input and utilize the internal address generated by the  
internal counter for fast interleaved memory applications. A  
port’s burst counter is loaded with the port’s Address Strobe  
(ADS). When the port’s Count Enable (CNTEN) is asserted,  
the address counter will increment on each LOW to HIGH  
transition of that port’s clock signal. This will read/write one  
word from/into each successive address location until CNTEN  
is deasserted. The counter can address the entire memory  
array and will loop back to the start. Counter Reset (CNTRST)  
is used to reset the burst counter.  
Each port contains a burst counter on the input address  
register. The internal write pulse width is independent of the  
LOW to HIGH transition of the clock signal. The internal write  
pulse is self-timed to allow the shortest possible cycle times.  
All parts are available in 100-pin Thin Quad Plastic Flatpack  
(TQFP) packages.  
Pin Configurations  
100-Pin TQFP (Top View)  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
A9L  
A10L  
A11L  
A12L  
A13L  
A14L  
A15L  
NC  
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A9R  
2
A10R  
A11R  
A12R  
A13R  
A14R  
A15R  
NC  
3
4
5
6
[7]  
[8]  
[7]  
[8]  
7
8
NC  
9
NC  
LBL  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
LBR  
UBL  
UBR  
CE0R  
CE1R  
CY7C09289V (64K x 16)  
CY7C09279V (32K x 16)  
CY7C09269V (16K x 16)  
CE0L  
CE1L  
CNTRSTL  
VCC  
CNTRSTR  
GND  
R/WL  
R/WR  
OEL  
OER  
FT/PIPEL  
FT/PIPER  
GND  
[9]  
[9]  
GND  
I/O15L  
I/O14L  
I/O13L  
I/O12L  
I/O15R  
I/O14R  
I/O13R  
I/O12R  
I/O11R  
I/O10R  
I/O11L  
I/O10L  
24  
25  
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
Notes:  
6. When writing simultaneously to the same location, the final value cannot be guaranteed.  
7. This pin is NC for CY7C09269V.  
8. This pin is NC for CY7C09269V and CY7C09279V.  
9. For CY7C09269V and CY7C09279V, pin #18 connected to V is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin  
CC  
compatible to an IDT 5V x16 flow-through device.  
Document #: 38-06056 Rev. *B  
Page 2 of 19  
1234567...19

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