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CY7C0241V PDF预览

CY7C0241V

更新时间: 2024-09-17 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
20页 255K
描述
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C0241V 数据手册

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1
CY7C024V/025V/026V  
PRELIMINARY  
CY7C0241V/0251V/036V  
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM  
• Automatic power-down  
Features  
• Expandable data bus to 32/36 bits or more using Mas-  
ter/Slave chip select when using more than one device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Pin select for Master or Slave  
• True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
• 4/8/16K x 16 organization (CY7C024V/025V/026V)  
• 4/8K x 18 organization (CY7C0241V/0251V)  
• 16K x 18 organization (CY7C036V)  
• 0.35-micron CMOS for optimum speed/power  
[1]  
• High-speed access: 15 /20/25 ns  
• Low operating power  
• Commercial and industrial temperature ranges  
• Available in 100-pin TQFP  
Active: I = 115 mA (typical)  
CC  
• Pin-compatible and functionally equivalent to  
IDT70V24, 70V25, and 7V0261.  
— Standby: I  
= 10 A (typical)  
µ
SB3  
• Fully asynchronous operation  
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
LB  
L
R
R
LB  
L
OE  
OE  
R
L
8/9  
8/9  
8/9  
8/9  
[2]  
[2]  
I/O  
–I/O  
I/O  
–I/O  
8/9L  
8/9L  
15/17L  
15/17R  
[3]  
I/O –I/O  
[3]  
I/O  
Control  
I/O  
Control  
I/O –I/O  
0L  
7/8L  
0L  
7/8R  
12/13/14  
12/13/14  
[4]  
[4]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A
A
–A  
A
A
–A  
11/12/13R  
0L  
0L  
11/1213L  
0R  
0R  
RAM Array  
12/13/14  
12/13/14  
–A[4]  
–A[4]  
11/12/13R  
11/12/13L  
CE  
CE  
OE  
Interrupt  
Semaphore  
Arbitration  
L
R
R
OE  
L
R/W  
R/W  
SEM  
L
R
R
SEM  
L
[5]  
[5]  
BUSY  
BUSY  
INT  
UB  
L
R
R
R
R
INT  
L
UB  
L
LB  
M/S  
LB  
L
Notes:  
1. Call for availability.  
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.  
3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.  
4. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.  
5. BUSY is an output in master mode and an input in slave mode.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 18, 1999  

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