Datasheet > 存储 > SRAM> CY62147VLL-70ZI

CY62147VLL-70ZI

更新时间： 2024-11-22 22:15:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
9页	173K
描述
4M (256K x 16) Static RAM

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CY62147VLL-70ZI 数据手册

CY62147V MoBL

4M (256K x 16) Static RAM

deselected (CE HIGH) or when CE is LOW and both BLE and

BHE are HIGH. The input/output pins (I/O₀through I/O₁₅) are

placed in a high-impedance state when: deselected (CE

HIGH), outputs are disabled (OE HIGH), BHE and BLE are

disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

Features

• Wide voltage range: 2.7V–3.6V

• Ultra-low active, standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₇). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₇).

• Package available in a standard 44-pin TSOP Type II

(forward pinout) package

Functional Description^[1]

The CY62147V is a high-performance CMOS static RAM

organized as 256K words by 16 bits. These devices feature

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life (MoBL^®) in

portable applications such as cellular telephones. The devices

also have an automatic power-down feature that significantly

reduces power consumption by 99% when addresses are not

toggling. The device can also be put into standby mode when

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

256K x 16

RAM Array

I/O – I/O

2048 x 2048

I/O – I/O

COLUMN DECODER

BHE

BLE

Power-down

Circuit

BHE

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05050 Rev. *A

Revised August 28, 2002

12 3 4 5 6 7...9

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与CY62147VLL-70ZI相关器件

型号	品牌	获取价格	描述	数据表
CY62147VLL-70ZIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PDSO44, TSOP2-44
CY62148	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148-100SC	ETC	获取价格	x8 SRAM
CY62148-100SI	ETC	获取价格	x8 SRAM
CY62148-100ZSC	ETC	获取价格	x8 SRAM
CY62148-100ZSI	ETC	获取价格	x8 SRAM
CY62148-55	CYPRESS	获取价格	512K x 8 Static RAM
CY62148-55SC	CYPRESS	获取价格	512K x 8 Static RAM
CY62148-70	CYPRESS	获取价格	512K x 8 Static RAM
CY62148-70SC	CYPRESS	获取价格	512K x 8 MoBL Static RAM

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