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CY62128

更新时间： 2024-11-04 22:56:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 254K
描述
128K x 8 Static RAM

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中文翻译

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CY62128 数据手册

 浏览型号CY62128的Datasheet PDF文件第2页浏览型号CY62128的Datasheet PDF文件第3页浏览型号CY62128的Datasheet PDF文件第4页浏览型号CY62128的Datasheet PDF文件第5页浏览型号CY62128的Datasheet PDF文件第6页浏览型号CY62128的Datasheet PDF文件第7页 
1CY62128  
fax id: 1072  
PRELIMINARY  
CY62128  
128K x 8 Static RAM  
feature that reduces power consumption by more than 75%  
when deselected.  
Features  
• 4.5V − 5.5V operation  
Writing to the device is accomplished by taking chip enable  
• CMOS for optimum speed/power  
• Low active power (70 ns, LL version)  
— 330 mW (max.) (60 mA)  
one (CE ) and write enable (WE) inputs LOW and chip enable  
1
two (CE ) input HIGH. Data on the eight I/O pins (I/O through  
2
0
I/O ) is then written into the location specified on the address  
7
pins (A through A ).  
0
16  
• Low standby power (70 ns, LL version)  
— 110 µW (max.) (20 µA)  
Reading from the device is accomplished by taking chip en-  
able one (CE ) and output enable (OE) LOW while forcing  
1
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE , CE , and OE options  
write enable (WE) and chip enable two (CE ) HIGH. Under  
2
these conditions, the contents of the memory location speci-  
fied by the address pins will appear on the I/O pins.  
1
2
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
Functional Description  
high-impedance state when the device is deselected (CE  
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or  
2
The CY62128 is a high-performance CMOS static RAM orga-  
nized as 131,072 words by 8 bits. Easy memory expansion is  
during a write operation (CE LOW, CE HIGH, and WE LOW).  
1
2
The CY62128 is available in a standard 400-mil-wide SOJ,  
525-mil wide (450-mil-wide body width) SOIC and 32-pin  
TSOP type I.  
provided by an active LOW chip enable (CE ), an active HIGH  
1
chip enable (CE ), an active LOW output enable (OE), and  
2
three-state drivers. This device has an automatic power-down  
Logic Block Diagram  
Pin  
Configurations  
Top View  
SOJ / SOIC  
V
NC  
32  
31  
30  
1
CC  
A
A
A
16  
14  
12  
A
15  
2
3
4
CE  
2
29  
28  
WE  
5
A
A
A
A
A
7
13  
8
27  
26  
6
6
I/O  
A
5
7
0
9
INPUT BUFFER  
25  
24  
23  
22  
21  
A
A
3
8
9
10  
11  
12  
13  
A
11  
4
OE  
I/O  
1
A
A
CE  
I/O  
I/O  
2
A
10  
0
A
1
1
A
1
A
2
A
7
6
0
0
I/O  
2
I/O  
I/O  
I/O  
20  
19  
A
3
4
I/O  
1
2
5
4
3
14  
15  
16  
A
I/O  
I/O  
I/O  
18  
17  
3
512 x 256 x 8  
ARRAY  
A
5
6
GND  
A
I/O  
4
A
7
8
A
A
1
2
32  
31  
OE  
11  
I/O  
5
A
A
A
A
9
8
10  
3
4
5
6
7
8
30  
29  
28  
CE  
1
I/O  
I/O  
I/O  
I/O  
13  
6
7
6
5
POWER  
DOWN  
COLUMN  
DECODER  
WE  
CE  
A
CE  
2
WE  
1
CE  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
2
I/O  
TSOP I  
7
15  
I/O  
I/O  
4
3
Top View  
V
CC  
62128-1  
(not to scale)  
NC  
A
9
GND  
OE  
I/O  
10  
11  
12  
13  
14  
15  
16  
16  
2
I/O  
1
I/O  
0
A
0
A
1
A
A
A
7
14  
12  
A
6
A
2
A
5
A
A
3
17  
4
62128-2  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
July 1996 - Revised November 1996  
12345678

中文翻译

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