Datasheet > CY621282BN

CY621282BN

更新时间： 2024-11-05 09:42:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	428K
描述
1-Mbit (128K x 8) Static RAM Automatic power-down when deselected

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CY621282BN 数据手册

CY621282BN

MoBL^Automotive

1-Mbit (128K x 8) Static RAM

Features

Functional Description

The CY621282BN^[1]is a high-performance CMOS static RAM

organized as 128K words by 8 bits. Easy memory expansion is

provided by an active LOW Chip Enable (CE₁), an active HIGH

Chip Enable (CE₂), and active LOW Output Enable (OE). This

device has an automatic power-down feature that reduces power

consumption by more than 75% when deselected.

■ Temperature Ranges

❐ Automotive-E: –40 °C to 125 °C

■ 4.5 V – 5.5 V operation

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed/power

Writing to the device is accomplished by taking Chip Enable One

(CE₁) and Write Enable (WE) inputs LOW and Chip Enable Two

(CE₂) input HIGH. Data on the eight I/O pins (I/O₀through I/O₇)

is then written into the location specified on the address pins (A₀

through A₁₆).

■ Low active power

137.5 mW (max.) (25 mA)

■ Low standby power

137.5 W (max.) (25 A)

Reading from the device is accomplished by taking Chip Enable

One (CE₁) and Output Enable (OE) LOW while forcing Write

Enable (WE) and Chip Enable Two (CE₂) HIGH. Under these

conditions, the contents of the memory location specified by the

address pins will appear on the I/O pins.

■ Automatic power-down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE₁, CE₂, and OE options

■ Available in Pb-free 32-pin (450 mil-wide) small outline

integrated circuit (SOIC) package

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE₁HIGH

or CE₂LOW), the outputs are disabled (OE HIGH), or during a

write operation (CE₁LOW, CE₂HIGH, and WE LOW).

Logic Block Diagram

I/O

INPUT BUFFER

I/O

128K x 8

ARRAY

I/O

POWER

DOWN

COLUMN

DECODER

Note

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-65526 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 6, 2011

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与CY621282BN相关器件

型号	品牌	获取价格	描述	数据表
CY621282BN_1106	CYPRESS	获取价格	1-Mbit (128 K x 8) Static RAM
CY621282BNLL-70SXE	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM Automatic power-down when deselected
CY621282BNLL-70SXET	CYPRESS	获取价格	Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, PLASTIC, SOIC-32
CY62128-55SC	CYPRESS	获取价格	128K x 8 Static RAM
CY62128-55VC	CYPRESS	获取价格	128K x 8 Static RAM
CY62128-55ZAC	ETC	获取价格	x8 SRAM
CY62128-55ZC	CYPRESS	获取价格	128K x 8 Static RAM
CY62128-70SC	CYPRESS	获取价格	128K x 8 Static RAM
CY62128-70SCT	CYPRESS	获取价格	Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, PLASTIC, SOIC-32
CY62128-70SI	ETC	获取价格	x8 SRAM

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