Datasheet > CY62127DV30L

CY62127DV30L

更新时间： 2022-11-24 21:45:01

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	375K
描述
1 Mb (64K x 16) Static RAM

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数据手册

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CY62127DV30L 数据手册

CY62127DV30

MoBL^®

Switching Characteristics (Over the Operating Range)^[11]

CY62127DV30-45 ^[8]CY62127DV30-55 CY62127DV30-70

Parameter

Read Cycle

t_RC

t_AA

t_OHA

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

Address to Data Valid

Data Hold from Address Change

CE LOW to Data Valid

t_ACE

t_DOE

OE LOW to Data Valid

OE LOW to Low Z^[12]

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

OE HIGH to High Z^[12,14]

CE LOW to Low Z^[12]

CE HIGH to High Z^[12,14]

CE LOW to Power-up

t_PD

CE HIGH to Power-down

BLE/BHE LOW to Data Valid

BLE/BHE LOW to Low Z^[12]

BLE/BHE HIGH to High-Z^[12,14]

t_DBE

t_LZBE

[13]

t_HZBE

Write Cycle^[15]

t_WC

t_SCE

t_AW

t_HA

t_SA

t_PWE

t_BW

t_SD

t_HD

t_HZWE

Write Cycle Time

CE LOW to Write End

Address Set-up to Write End

Address Hold from Write End

Address Set-up to Write Start

WE Pulse Width

BLE/BHE LOW to Write End

Data Set-up to Write End

Data Hold from Write End

WE LOW to High Z^[12,14]

WE HIGH to Low Z^[12]

t_LZWE

Notes:

11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V

/2, input pulse levels of 0 to V

, and output loading of the

CC(typ.)

specified I

12. At any given temperature and voltage condition, t

given device.

is less than t

, t

is less than t

, t

is less than t

, and t

is less than t

for any

LZWE

HZCE

LZCE HZBE

LZBE HZOE

LZOE

HZWE

13. If both byte enables are toggled together, this value is 10 ns.

14. t

, t

, and t

transitions are measured when the outputs enter a high-impedance state.

HZOE HZCE HZBE

HZWE

15. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any

of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates

the write.

Document #: 38-05229 Rev. *D

Page 5 of 12

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