Datasheet > CY62127DV20

CY62127DV20

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	217K
描述
1M (64K x 16) Static RAM

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CY62127DV20 数据手册

CY62127DV20

MoBL2^®

ADVANCE

INFORMATION

AC Test Loads and Waveforms

ALL INPUT PULSES

V_CC

V_CCTyp

90%

UTPUT

10%

GND

C_L= 30 p F

Rise Tim e :

1 V/ ns

Fa ll Tim e :

1 V/ ns

INCLUDING

JIG AND

SCOPE

Eq uiva le nt to :

THÉVENIN EQUIVALENT

R_TH

OUTPUT

Pa ra m e te rs

1.8V

1350 0

1080 0

6000

UNIT

Ω

R 1

R 2

Ω

R _TH

V_TH

Ω

0.80

Data Retention Characteristics

Parameter

V_DR

I_CCDR

Description

V_CCfor Data Retention

Data Retention Current

Conditions

Min.

Typ.^[4]

Max.

2.2

Unit

V_CC= 1V, CE₁> V_CC− 0.2V, CE₂<

0.2V, V_IN> V_CC− 0.2V or V_IN< 0.2V

µA

TBD

[5]

t_CDR

Chip Deselect to Data Reten-

tion Time

[6]

t_R

Operation Recovery Time

t_RC

Data Retention Waveform^[7]

DATA RETENTION MODE

V_{CC(m in.)}

t_R

V_DR> 1.0V

V_{CC(m in.)}

t_CDR

CE₁o r

BHE BLE

o r

Notes:

6. Full device operation requires linear V_CCramp from V_DRto V_CC(min.)> 100 µs or stable at V_CC(min.)> 100 µs.

7. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both.

Document #: 38-05301 Rev. **

Page 5 of 12

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