Datasheet > CY62127DV20

CY62127DV20

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	217K
描述
1M (64K x 16) Static RAM

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数据手册

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CY62127DV20 数据手册

CY62127DV20

MoBL2^®

ADVANCE

INFORMATION

Switching Waveforms (continued)

Write Cycle No. 2 (CE₁or CE₂Controlled) ^{[12, 16, 17, 18]}

t_WC

ADDRESS

t _SCE

t _SA

t_AW

t _HA

t _PWE

t_BW

BHE /BLE

t_SD

t _HD

VALID

DATA I/ O

DATA

DON’T CARE

t_HZOE

Write Cycle No. 3 (WE Controlled, OE LOW)^{[17, 18]}

t_WC

ADDRESS

t_SCE

CE₁

CE₂

t_AW

t_HA

t_SA

t_PWE

t_SD

DATA_INVALID

t_HD

DON’T CARE

DATA I/ O

t_LZWE

t_HZWE

Notes:

16. Data I/O is high-impedance if OE = V_IH

17. If CE₁goes HIGH or CE₂goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.

18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Document #: 38-05301 Rev. **

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