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CY28400ZXC-2 PDF预览

CY28400ZXC-2

更新时间： 2024-01-06 10:41:10
品牌 Logo 应用领域
SPECTRALINEAR 逻辑集成电路光电二极管驱动PC
页数 文件大小 规格书
15页 238K
描述
100 MHz Differential Buffer for PCI Express and SATA

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CY28400ZXC-2 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：TSSOP包装说明：4.40 MM, LEAD FREE, MO-153, TSSOP-28
针数：28Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.54
系列：28400输入调节：DIFFERENTIAL
JESD-30 代码：R-PDSO-G28JESD-609代码：e3
长度：9.7 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：28
实输出次数：4最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：4.5 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：1.1 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：4.4 mm
Base Number Matches：1

CY28400ZXC-2 数据手册

 浏览型号CY28400ZXC-2的Datasheet PDF文件第4页浏览型号CY28400ZXC-2的Datasheet PDF文件第5页浏览型号CY28400ZXC-2的Datasheet PDF文件第6页浏览型号CY28400ZXC-2的Datasheet PDF文件第8页浏览型号CY28400ZXC-2的Datasheet PDF文件第9页浏览型号CY28400ZXC-2的Datasheet PDF文件第10页 
CY28400-2  
Table 4. Buffer Power-up State Machine  
State  
Description  
0
1
3.3V Buffer power off  
After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay  
2[1]  
Buffer waits for PWRDWN deassertion (and waits for a valid clock on the SRC_IN input in PLL mode)  
3[2,3,4] Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation  
Figure 5. Buffer Power-up State Diagram  
SRC_STP Clarification  
SRC_STP Assertion  
The SRC_STP signal is an asynchronous input used for clean  
stopping and starting the DIFT/C outputs. This input can be  
Active HIGH or Active LOW based on the strapped value of  
the OE_INV input. The SRC_STP signal is a debounced signal  
in that its state must remain unchanged during two consec-  
utive rising edges of DIFC to be recognized as a valid  
assertion or deassertion. (The assertion and deassertion of  
this signal is absolutely asynchronous.) In the case where the  
output is disabled via OE control, the output will always be  
tri-stated regardless of the SRC_STP Drive Mode register bit  
state.  
The impact of asserting the SRC_STP pin is that all DIF  
outputs that are set in the control registers to stoppable via  
assertion of SRC_STP are stopped after their next transition.  
When the control register SRC_STP tri-state bit is  
programmed to ‘0’, the final state of all stopped DIFT/C signals  
is DIFT clock = High and DIFC = Low. There will be no change  
to the output drive current values, DIFT will be driven high with  
a current value equal 6 x Iref, and DIFC will not be driven.  
When the control register SRC_STP three-state bit is  
programmed to ‘1’, the final state of all stopped DIF signals is  
low, both DIFT clock and DIFC clock outputs will not be driven.  
Table 5. SRC_STP Functionality[4]  
OE_INV  
SRC_STP  
DIFT  
Normal  
DIFC  
Normal  
Low  
0
0
1
1
1
0
1
0
Iref * 6 or Float  
Iref * 6 or Float  
Normal  
Low  
Normal  
Notes:  
1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN is an undefined mode and not recommended. Operation in this mode may result in glitches  
excessive frequency shifting.  
2. The total power up latency from power-on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input).  
3. In PLL Mode, if power is valid and PWRDWN is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid  
input clocks are detected, valid power, PWRDWN deasserted with the PLL locked and stable, are the DIF outputs enabled.  
4. In the case where OE is asserted low, the output will always be three-stated regardless of SRC_STP drive mode register bit state.  
Rev 1.0,November 21, 2006  
Page 7 of 15  
1...45678910...15

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