Datasheet > CY28405

CY28405

更新时间： 2024-01-11 02:30:10

品牌	Logo	应用领域
SPECTRALINEAR		时钟
页数	文件大小	规格书
18页	198K
描述
CK409-Compliant Clock Synthesizer

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中文翻译

获取价格

技术参数
数据手册

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CY28405 技术参数

是否无铅：	不含铅	生命周期：	Active
零件包装代码：	SSOP	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.27
Is Samacsys：	N	Base Number Matches：	1

CY28405 数据手册

CY28405

CK409-Compliant Clock Synthesizer

• Three differential CPU clock pairs

• Dial-A-Frequency^®

• Supports SMBus/I²C Byte, Word, and Block Read/Write

Features

• Supports Intel^£Springdale/Prescott (CK409)

• Selectable CPU frequencies

• 3.3V power supply

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Nine copies of PCI clock

• 48-pin SSOP package

• Four copies 3V66 clock with one optional VCH

• Two copies 48 MHz USB clock

• Two copies REF clock

CPU

x 3

3V66

x 4

PCI

x 9

REF

x 2

48M

x 2

Block Diagram

Pin Configuration

**FS_A/REF_0

VDDA

VSSA

IREF

CPUT_ITP

CPUC_ITP

VSS_CPU

CPUT1

CPUC1

VDD_CPU

CPUT0

CPUC0

VSS

DNC***

VDD

VTT_PWRGD#

SDATA

SCLK

3V66_0

3V66_1

VSS_3V66

VDD_3V66

3V66_2/MODE*

3V66_3/VCH/SELVCH**

**FS_B/REF_1

VDD_REF

XIN

VDD_REF

XIN

XTAL

OSC

REF[0:1]

XOUT

PLL Ref Freq

XOUT

VSS_REF

VDD_CPU

CPUT[0:1,ITP], CPUC[0:1,ITP]

Divider

*FS_C/PCIF0

PLL 1

Network

*FS_D/PCIF1

*FS_E/PCIF2

VDD_PCI

VSS_PCI

PCI0

FS_[A:E]

VTT_PWRGD#

IREF

PCI1

PCI2

PCI3

VDD_3V66

3V66_[0:2]

VDD_PCI

PCIF[0:2]

VDD_PCI

VSS_PCI

PCI4

PLL2

SELVCH

PCI[0:5]

PCI5

MODE

RESET#/PD#

DOT_48

USB_48

VSS_48

VDD_48

3V66_3/VCH

VDD_48MHz

DOT_48

PD#

USB_48

SSOP-48

* 150k Internal Pull-up

** 150k Internal Pull-down

*** Do Not Connect

SDATA

SCLK

I C

Logic

Timer

RESET#

Rev 1.0, November 20, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 18

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

12 3 4 5 6 7...18

中文翻译

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