CY23S09SXC-1H

更新时间： 2024-11-20 04:38:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	189K
描述
Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer

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技术参数
数据手册
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CY23S09SXC-1H 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	Factory Lead Time：	1 week
风险等级：	1.68	系列：	23S
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4	长度：	9.893 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.012 A
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	8	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	传播延迟（tpd）：	0.35 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.25 ns
座面最大高度：	1.727 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.8989 mm
最小 fmax：	133.33 MHz	Base Number Matches：	1

CY23S09SXC-1H 数据手册

CY23S09

CY23S05

Low-Cost 3.3V Spread Aware™ Zero Delay Buffer

up to 100-/133-MHz frequencies, and have higher drive than

the -1 devices. All parts have on-chip PLLs that lock to an input

Features

• 10-MHz to 100-/133-MHz operating range, compatible

clock on the REF pin. The PLL feedback is on-chip and is

with CPU and PCI bus frequencies

obtained from the CLKOUT pad.

• Zero input-output propagation delay

• Multiple low-skew outputs

— Output-output skew less than 250 ps

— Device-device skew less than 700 ps

— One input drives five outputs (CY23S05)

The CY23S09 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the Select Input

Decoding table on page 2. If all output clocks are not required,

Bank B can be three-stated. The select inputs also allow the

input clock to be directly applied to the outputs for chip and

system testing purposes.

The CY23S09 and CY23S05 PLLs enter a power-down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0 µA of current draw (for commercial temper-

ature devices) and 25.0 µA (for industrial temperature

devices). The CY23S09 PLL shuts down in one additional

case, as shown in the table below.

Multiple CY23S09 and CY23S05 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

All outputs have less than 200 ps of cycle-to-cycle jitter. The

input to output propagation delay on both devices is

guaranteed to be less than 350 ps, and the output to output

skew is guaranteed to be less than 250 ps.

— One input drives nine outputs, grouped as 4 + 4 + 1

(CY23S09)

• Less than 200 ps cycle-to-cycle jitter is compatible with

Pentium^-based systems

• Test Mode to bypass PLL (CY23S09 only, see Select

Input Decoding table on page 2)

• Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm

TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil

SOIC package (CY23S05)

• 3.3V operation, advanced 0.65µ CMOS technology

• Spread Aware™

Functional Description

The CY23S05/CY23S09 is available in two different configu-

rations, as shown in the ordering information on page 6. The

CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/

CY23S09-1H is the high-drive version of the -1, and its rise

and fall times are much faster than -1.

The CY23S09 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC

package. The CY23S05 is an eight-pin version of the

CY23S09. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at

Block Diagram

Pin Configuration

SOIC/TSSOP/SSOP

CLKOUT

PLL

Top View

MUX

REF

CLKA1

CLKA2

REF

CLKA1

CLKA2

CLKOUT

CLKA4

CLKA3

CLKA4

GND

CLKB4

CLKB3

GND

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

CLKB2

CY23S09

SOIC

REF

PLL

CLKOUT

CLK1

Top View

CLKOUT

CLK4

REF

CLK2

CLK3

CLK2

CLK1

CLK3

GND

CLK4

CY23S05

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07296 Rev. *C

Revised September 21, 2004

12 3 4 5 6 7...9

中文翻译

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CY23S09SXC-1H 替代型号

型号	品牌	替代类型	描述	数据表
CY2309SXI-1	CYPRESS	类似代替	Low-Cost 3.3V Zero Delay Buffer
CY2308SXI-2	CYPRESS	类似代替	3.3V Zero Delay Buffer
CY2308SXI-1H	CYPRESS	类似代替	3.3V Zero Delay Buffer

与CY23S09SXC-1H相关器件

型号	品牌	获取价格	描述	数据表
CY23S09SXC-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY23S09SXC-1T	CYPRESS	获取价格	PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY23S09ZC-1	CYPRESS	获取价格	Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer
CY23S09ZC-1H	CYPRESS	获取价格	Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer
CY23S09ZXC-1	CYPRESS	获取价格	Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer
CY23S09ZXC-1H	CYPRESS	获取价格	Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer
CY23S09ZXC-1H	INFINEON	获取价格	Low Cost 3.3V Spread Aware Zero Delay Buffer
CY23S09ZXC-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2410	CYPRESS	获取价格	MPEG Clock Generator with VCXO Integrated phase-locked loop (PLL)
CY2410-1	CYPRESS	获取价格	MPEG Clock Generator with VCXO Integrated phase-locked loop (PLL)

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