5秒后页面跳转
CY2309C PDF预览

CY2309C

更新时间: 2024-02-02 18:48:30
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
3页 152K
描述
Zero Delay Buffers

CY2309C 数据手册

 浏览型号CY2309C的Datasheet PDF文件第2页浏览型号CY2309C的Datasheet PDF文件第3页 
CY2305C  
CY2309C  
Errata Revision: [**]  
May 10, 2007  
Errata Document for CY2305C, CY2309C Zero Delay Buffers  
This document describes the errata for the Zero Delay Clock Buffers, CY2305C and CY2309C. Details include errata  
trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document  
to the device’s data sheet for a complete functional description.  
Contact your local Cypress Sales Representative if you have questions.  
Part Numbers Affected  
Part Number  
CY2305C-1  
CY2305C-1H  
CY2309C-1  
CY2309C-1H  
Temperature Grades  
Packages  
all  
all  
all  
all  
all  
all  
all  
all  
Zero Delay Buffer Qualification Status  
In Production  
Zero Delay Buffer Errata Summary  
The following table defines the errata applicability to available Zero Delay Buffer family devices.  
Note Errata titles are hyperlinked. Click on the table item entry to jump to its description.  
Items  
Part Numbers  
Fix Status  
[1] Possible increased power down current  
All  
Will be corrected in the next silicon revision. The  
errata is forecast to be corrected for all devices  
dated October 2007 and later.  
1. Possible increased power down current  
• PROBLEM DEFINITION  
When the device is in the power down state, an unbonded pad on the die is allowed to float. Because of this,  
power down current may exceed the data sheet limit.  
While high current draw is theoretically possible any time during power down, it has only been observed as a  
transient occurrence shortly after the device enters power down. Steady-state current has always been ob-  
served to be within data sheet limits.  
• PARAMETERS AFFECTED  
Parameter  
Temperature Range  
Commercial  
Data Sheet Maximum  
Actual Maximum  
3.5 mA  
IDD (PD Mode)  
12 µA  
25 µA  
Industrial  
3.5 mA  
• TRIGGER CONDITION(S)  
None.  
Cypress Semiconductor Corporation  
Document Number: 001-15585 Rev. **  
198 Champion Court  
San Jose, CA 95134  
408.943.2600  
Revised May 10, 2007  

与CY2309C相关器件

型号 品牌 获取价格 描述 数据表
CY2309C-1 CYPRESS

获取价格

Zero Delay Buffers
CY2309C-1H CYPRESS

获取价格

Zero Delay Buffers
CY2309CSXC-1 CYPRESS

获取价格

3.3V Zero Delay Clock Buffer
CY2309CSXC-1H CYPRESS

获取价格

3.3V Zero Delay Clock Buffer
CY2309CSXC-1H INFINEON

获取价格

3.3V Zero Delay Buffer
CY2309CSXC-1HT INFINEON

获取价格

3.3V Zero Delay Buffer
CY2309CSXC-1HT CYPRESS

获取价格

3.3V Zero Delay Clock Buffer
CY2309CSXC-1T CYPRESS

获取价格

3.3V Zero Delay Clock Buffer
CY2309CSXI-1 CYPRESS

获取价格

3.3V Zero Delay Clock Buffer
CY2309CSXI-1H CYPRESS

获取价格

3.3V Zero Delay Clock Buffer