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CY22388ZXC-XXX

更新时间: 2024-12-01 03:11:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路石英晶振压控振荡器光电二极管
页数 文件大小 规格书
10页 297K
描述
Factory Programmable Quad PLL Clock Generator with VCXO

CY22388ZXC-XXX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.77
Is Samacsys:NJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:3端子数量:16
最高工作温度:70 °C最低工作温度:-10 °C
最大输出时钟频率:166 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:100 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY22388ZXC-XXX 数据手册

 浏览型号CY22388ZXC-XXX的Datasheet PDF文件第2页浏览型号CY22388ZXC-XXX的Datasheet PDF文件第3页浏览型号CY22388ZXC-XXX的Datasheet PDF文件第4页浏览型号CY22388ZXC-XXX的Datasheet PDF文件第5页浏览型号CY22388ZXC-XXX的Datasheet PDF文件第6页浏览型号CY22388ZXC-XXX的Datasheet PDF文件第7页 
CY22388/89/91  
Factory Programmable Quad PLL  
Clock Generator with VCXO  
Benefits  
Features  
Fully integrated phase-locked loops (PLLs)  
QFN package:  
Meets most Digital Set Top Box, DVD Recorder, and DTV  
application requirements  
Multiple high-performance PLLs allow synthesis of  
unrelated frequencies  
40% smaller than 20-pin TSSOP  
22% smaller than 16-pin TSSOP  
Selectable Output Frequency  
Programmable Output Frequencies  
• Output Frequency Range of 5–166 MHz  
Input Frequency Range  
Integration eliminates the need for external loop filter  
components  
Meets critical timing requirements in complex system  
designs  
Enables application compatibility  
• Crystal: 10–30 MHz  
Complete VCXO solution with ±120 ppm (typical pull range)  
• External Reference: 1–100 MHz  
Analog VCXO  
16-/20-pin TSSOP and 32-pin QFN packages  
3.3V operation with 2.5V output buffer option  
Block Diagram  
CLKA  
CLKB  
CLKC  
PLL1  
XIN  
VCXO  
PLL2  
PLL3  
PLL4  
XOUT  
VIN  
CLKD  
Divider  
&
Multiplexer  
CLKE  
CLKF  
CLKG  
CLKH  
FS0/1/2  
OE  
Select  
Logic  
Pin Configurations  
32-Pin Q FN  
20-Pin TSSOP  
20  
XIN  
FS0  
1
XOUT  
VDD  
OE/PD  
FS2  
16-Pin TSSO P  
2
3
4
5
6
7
8
19  
18  
17  
16  
15  
14  
XIN  
FS0  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
XOUT  
VDD  
1
2
3
4
5
6
7
8
24  
V IN  
OE /PD #  
FS1  
23 FS 2  
VD D  
VD D  
CLKH  
VDD  
VSS  
22  
FS1  
FS2  
V D D  
V SS  
21 V D D  
VIN  
VDD  
VIN  
C Y22391  
CY22388  
CY22389  
20  
V SS  
V SS  
VS S  
VDD  
VSS  
CLKA  
CLKB  
VSS  
VDD  
VSS  
19 VS S  
18 C LK G  
17 C LK F  
CLKE  
CLKD  
CLKC  
CLKD  
V SS  
CLKB  
CLKA  
CLKC  
13  
12  
CLKG  
CLKF  
CLKE  
C LKH  
9
10  
11  
Cypress Semiconductor Corporation  
Document #: 38-07734 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 10, 2006  
[+] Feedback  

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