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CY22381SXC-XXXT PDF预览

CY22381SXC-XXXT

更新时间: 2024-12-01 06:51:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器闪存微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
9页 346K
描述
Three-PLL General Purpose FLASH Programmable Clock Generator

CY22381SXC-XXXT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.31
Is Samacsys:NJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.889 mm
湿度敏感等级:3端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:166 MHz认证状态:Not Qualified
座面最大高度:1.7272 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:3.8985 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY22381SXC-XXXT 数据手册

 浏览型号CY22381SXC-XXXT的Datasheet PDF文件第2页浏览型号CY22381SXC-XXXT的Datasheet PDF文件第3页浏览型号CY22381SXC-XXXT的Datasheet PDF文件第4页浏览型号CY22381SXC-XXXT的Datasheet PDF文件第5页浏览型号CY22381SXC-XXXT的Datasheet PDF文件第6页浏览型号CY22381SXC-XXXT的Datasheet PDF文件第7页 
CY22381  
Three-PLL General Purpose FLASH  
Programmable Clock Generator  
Improves frequency accuracy over temperature, age, process,  
and initial offset  
Features  
Three integrated phase-locked loops  
Non-volatile programming enables easy customization,  
ultra-fast turnaround, performance tweaking, design timing  
margin testing, inventory control, lower part count, and more  
secureproductsupply. Canalsobeprogrammedmultipletimes  
which reduces programming errors and provides an easy  
upgrade path for existing designs  
Ultra-wide divide counters (eight-bit Q, eleven-bit P, and  
seven-bit post divide)  
Improved linear crystal load capacitors  
Flash programmability  
In-house programming of samples and prototype quantities is  
available using the CY3672 FTG development Kit. Production  
quantities are available through Cypress’s value-added  
distribution partners or by using third party programmers from  
BP Microsystems, HiLo Systems, and others.  
Field programmability  
Low-jitter, high-accuracy outputs  
Power-management options (Shutdown, OE, Suspend)  
Configurable crystal drive strength  
Frequency select option through external LVTTL Input  
3.3V operation  
Performance suitable for high-end multimedia,  
communications, industrial, A/D converters, and consumer  
applications  
Supports numerous low-power application schemes and  
reduces EMI by allowing unused outputs to be turned off  
Eight-pin SOIC package  
CyClocks RT™ support  
Adjust crystal drive strength for compatibility with virtually all  
crystals  
Benefits  
External frequency select option for PLL1, CLKA, and CLKB  
Generates up to three unique frequencies on three outputs up  
to 200 MHz from an external source. Functional upgrade for  
current CY2081 family.  
Industry standard supply voltage  
Industry standard packaging saves on board space  
Easy-to-use software support for design entry  
Allows for 0 ppm frequency generation and frequency  
conversion under the most demanding applications  
Logic Block Diagram  
XTALIN  
OSC.  
XTALOUT  
PLL1  
Divider  
7-BIT  
CLKC  
11-BIT P  
8-BIT Q  
CONFIGURATION  
FLASH  
4 × 3  
Crosspoint  
Switch  
PLL2  
Divider  
7-BIT  
11-BIT P  
8-BIT Q  
CLKB  
CLKA  
SHUTDOWN/OE  
FS/SUSPEND  
PLL3  
Divider  
7-BIT  
11-BIT P  
8-BIT Q  
Cypress Semiconductor Corporation  
Document #: 38-07012 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 10, 2008  
[+] Feedback  

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