Datasheet > CY15B104QN-50LPXIT

CY15B104QN-50LPXIT

更新时间： 2023-12-06 20:00:03

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
42页	591K
描述
4Mb 3.3V Industrial 50MHz SPI EXCELON? F-RAM in 8-pin GQFN

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CY15B104QN-50LPXIT 数据手册

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4-Mb EXCELON™ LP Ferroelectric RAM (F-RAM)

Serial (SPI), 512K × 8, industrial

Functional overview

3.3

Terms used in SPI protocol

The commonly used terms in the SPI protocol are as follows:

3.3.1

SPI master

The SPI master device controls the operations on the SPI bus. An SPI bus may have only one master with one or

more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices

using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS

pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are

synchronized with this clock.

3.3.2

SPI slave

The SPI slave device is activated by the master through the chip select line. A slave device gets the SCK as an input

from the SPI master and all the communication is synchronized with this clock. An SPI slave never initiates a

communication on the SPI bus and acts only on the instruction from the master.

The CY15X104QN operates as an SPI slave and may share the SPI bus with other SPI slave devices.

3.3.3

Chip select (CS)

To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued

to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored

and the serial output pin (SO) remains in a high-impedance state.

Note: A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each

active chip select cycle.

3.3.4

Serial clock (SCK)

The serial clock is generated by the SPI master and the communication is synchronized with this clock after CS

goes LOW.

The CY15X104QN supports SPI modes 0 and 3 for data communication. In both of these modes, the inputs are

latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the

first rising edge of SCK signifies the arrival of the first most significant Bit (MSb) of an SPI instruction on the SI pin.

Further, all data inputs and outputs are synchronized with SCK.

Datasheet

002-19436 Rev. *O

2023-06-05

1...4 5 678 9 10...42

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