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CY15B016Q-SXAT PDF预览

CY15B016Q-SXAT

更新时间: 2024-03-03 10:11:29
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英飞凌 - INFINEON 存储
页数 文件大小 规格书
20页 600K
描述
铁电存储器 (F-RAM)

CY15B016Q-SXAT 数据手册

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CY15B016Q  
edge of SCK starting from the first rising edge after CS goes  
active.  
Functional Overview  
The CY15B016Q is a serial F-RAM memory. The memory array  
is logically organized as 2,048 × 8 bits and is accessed using an  
industry standard serial peripheral interface (SPI) bus. The  
functional operation of the F-RAM is similar to serial flash and  
serial EEPROMs. The major difference between the  
CY15B016Q and a serial flash or EEPROM with the same pinout  
is the F-RAM's superior write performance, high endurance, and  
low power consumption.  
The SPI protocol is controlled by opcodes. These opcodes  
specify the commands from the bus master to the slave device.  
After CS is activated, the first byte transferred from the bus  
master is the opcode. Following the opcode, any addresses and  
data are then transferred. The CS must go inactive after an  
operation is complete and before a new opcode can be issued.  
The commonly used terms in the SPI protocol are as follows:  
SPI Master  
Memory Architecture  
The SPI master device controls the operations on a SPI bus. An  
SPI bus may have only one master with one or more slave  
devices. All the slaves share the same SPI bus lines and the  
master may select any of the slave devices using the CS pin. All  
of the operations must be initiated by the master activating a  
slave device by pulling the CS pin of the slave LOW. The master  
also generates the SCK and all the data transmission on SI and  
SO lines are synchronized with this clock.  
When accessing the CY15B016Q, the user addresses 2K  
locations of eight data bits each. These eight data bits are shifted  
in or out serially. The addresses are accessed using the SPI  
protocol, which includes a chip select (to permit multiple devices  
on the bus), an opcode, and a two-byte address. The upper 5 bits  
of the address range are 'don't care' values. The complete  
address of 11 bits specifies each byte address uniquely.  
Most functions of the CY15B016Q are either controlled by the  
SPI interface or handled by on-board circuitry. The access time  
for the memory operation is essentially zero, beyond the time  
needed for the serial protocol. That is, the memory is read or  
written at the speed of the SPI bus. Unlike a serial flash or  
EEPROM, it is not necessary to poll the device for a ready  
condition because writes occur at bus speed. By the time a new  
bus transaction can be shifted into the device, a write operation  
is complete. This is explained in more detail in the interface  
section.  
SPI Slave  
The SPI slave device is activated by the master through the Chip  
Select line. A slave device gets the SCK as an input from the SPI  
master and all the communication is synchronized with this  
clock. An SPI slave never initiates a communication on the SPI  
bus and acts only on the instruction from the master.  
The CY15B016Q operates as an SPI slave and may share the  
SPI bus with other SPI slave devices.  
Chip Select (CS)  
Note The CY15B016Q contains no power management circuits  
other than a simple internal power-on reset circuit. It is the user’s  
responsibility to ensure that VDD is within datasheet tolerances  
to prevent incorrect operation. It is recommended that the part is  
not powered down with chip enable active.  
To select any slave device, the master needs to pull down the  
corresponding CS pin. Any instruction can be issued to a slave  
device only while the CS pin is LOW. When the device is not  
selected, data through the SI pin is ignored and the serial output  
pin (SO) remains in a high-impedance state.  
Serial Peripheral Interface – SPI Bus  
Note A new instruction must begin with the falling edge of CS.  
Therefore, only one opcode can be issued for each active Chip  
Select cycle.  
The CY15B016Q is a SPI slave device and operates at speeds  
up to 20 MHz. This high-speed serial bus provides  
high-performance serial communication to a SPI master. Many  
common microcontrollers have hardware SPI ports allowing a  
direct interface. It is quite simple to emulate the port using  
ordinary port pins for microcontrollers that do not. The  
CY15B016Q operates in SPI Mode 0 and 3.  
Serial Clock (SCK)  
The Serial Clock is generated by the SPI master and the  
communication is synchronized with this clock after CS goes  
LOW.  
The CY15B016Q enables SPI modes 0 and 3 for data  
communication. In both of these modes, the inputs are latched  
by the slave device on the rising edge of SCK and outputs are  
issued on the falling edge. Therefore, the first rising edge of SCK  
signifies the arrival of the first bit (MSB) of a SPI instruction on  
the SI pin. Further, all data inputs and outputs are synchronized  
with SCK.  
SPI Overview  
The SPI is a four-pin interface with Chip Select (CS), Serial Input  
(SI), Serial Output (SO), and Serial Clock (SCK) pins.  
The SPI is a synchronous serial interface, which uses clock and  
data pins for memory access and supports multiple devices on  
the data bus. A device on the SPI bus is activated using the CS  
pin.  
Data Transmission (SI/SO)  
The relationship between chip select, clock, and data is dictated  
by the SPI mode. This device supports SPI modes 0 and 3. In  
both of these modes, data is clocked into the F-RAM on the rising  
The SPI data bus consists of two lines, SI and SO, for serial data  
communication. SI is also referred to as Master Out Slave In  
(MOSI) and SO is referred to as Master In Slave Out (MISO). The  
master issues instructions to the slave through the SI pin, while  
Document Number: 002-10216 Rev. *B  
Page 4 of 20  

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