Datasheet > CY14E102L-BA20XIT

CY14E102L-BA20XIT

更新时间： 2024-11-18 06:51:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
21页	617K
描述
2-Mbit (256K x 8/128K x 16) nvSRAM

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ADVANCE

CY14E102L, CY14E102N

2-Mbit (256K x 8/128K x 16) nvSRAM

Features

Functional Description

■ 15 ns, 20 ns, 25 ns, and 45 ns access times

The Cypress CY14E102L/CY14E102N is a fast static RAM, with

a nonvolatile element in each memory cell. The memory is

■ Internally organized as 256K x 8 (CY14E102L) or 128K x 16

(CY14E102N)

organized as 256K words of 8 bits each or 128K words of 16 bits

each. The embedded nonvolatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data reside in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both the STORE and RECALL operations are also available

under software control.

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap^™nonvolatile elements initiated by

software, device pin, or AutoStore^™on power down

■ RECALL to SRAM initiated by software or power up

■ Infinite read, write, and recall cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 5V +10% operation

■ Commercial and Industrial temperatures

■ 48-pin FBGA, 44 and 54-pin TSOP II packages

■ Pb-free and RoHS compliance

Logic Block Diagram

CAP

[1]

A - A

Address

[1]

DQ0 - DQ7

CY14E102L

CY14E102N

HSB

BHE

BLE

Note

1. Address A - A and Data DQ0 - DQ7 for x8 configuration, Address A - A and Data DQ0 - DQ15 for x16 configuration.

Cypress Semiconductor Corporation

Document Number: 001-45755 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 27, 2008

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