Datasheet > CY14B104LA

CY14B104LA

更新时间： 2022-12-28 02:38:14

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
23页	845K
描述
4 Mbit (512K x 8/256K x 16) nvSRAM

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数据手册

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CY14B104LA 数据手册

CY14B104LA, CY14B104NA

4 Mbit (512K x 8/256K x 16) nvSRAM

Features

Functional Description

■ 20 ns, 25 ns, and 45 ns Access Times

The Cypress CY14B104LA/CY14B104NA is a fast static RAM,

with a nonvolatile element in each memory cell. The memory is

■ Internally Organized as 512K x 8 (CY14B104LA) or 256K x 16

(CY14B104NA)

organized as 512K bytes of 8 bits each or 256K words of 16 bits

each. The embedded nonvolatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data resides in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both the STORE and RECALL operations are also available

under software control.

■ Hands Off Automatic STORE on Power Down with only a Small

Capacitor

■ STORE to QuantumTrap Nonvolatile Elements Initiated by

Software, Device Pin, or AutoStore on Power Down

■ RECALL to SRAM Initiated by Software or Power Up

■ Infinite Read, Write, and Recall Cycles

■ 200,000 STORE Cycles to QuantumTrap

■ 20 year Data Retention

■ Single 3V +20%, -10% Operation

■ Commercial and Industrial Temperatures

■ 48-Ball FBGA and 44/54-Pin TSOP-II Packages

■ Pb-free and RoHS Compliance

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Notes

1. Address A - A for x8 configuration and Address A - A for x16 configuration.

2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.

3. BHE and BLE are applicable for x16 configuration only.

Cypress Semiconductor Corporation

Document #: 001-49918 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 22, 2009

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