CXK77K36R320GB-4 PDF预览

CXK77K36R320GB-4

更新时间: 2025-08-11 02:51:51
品牌 Logo 应用领域
索尼 - SONY 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
22页 177K
描述
32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)

CXK77K36R320GB-4 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
Is Samacsys:N最长访问时间:2 ns
最大时钟频率 (fCLK):250 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:37748736 bit
内存集成电路类型:LATE-WRITE SRAM内存宽度:36
功能数量:1端子数量:119
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:1MX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA119,7X17,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:1.5,2.5 V认证状态:Not Qualified
座面最大高度:2.4 mm最大待机电流:0.18 A
最小待机电流:2.38 V子类别:SRAMs
最大压摆率:0.65 mA最大供电电压 (Vsup):2.63 V
最小供电电压 (Vsup):2.37 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN LEAD
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:10
宽度:14 mmBase Number Matches:1

CXK77K36R320GB-4 数据手册

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SONY  
CXK77K36R320GB  
3/33/4  
32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)  
Preliminary  
Description  
The CXK77K36R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words  
by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer  
onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro-  
viding a high-performance user interface.  
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K  
differential input clock.  
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.  
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.  
Sleep (power down) capability is provided via the ZZ input signal.  
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external  
control resistor RQ between ZQ and V , the impedance of the output drivers can be precisely controlled.  
SS  
333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of  
IEEE standard 1149.1 protocol.  
Features  
3 Speed Bins  
Cycle Time / Access Time  
3.0ns / 1.6ns  
-3  
-33  
-4  
3.3ns / 1.6ns  
4.0ns / 2.0ns  
Single 2.5V power supply (V ): 2.5V ± 5%  
DD  
Note: 1.8V V is also supported. Please contact Sony Memory Marketing Department for further information.  
DD  
Dedicated output supply voltage (V  
): 1.5V ± 0.1V  
DDQ  
Note: 1.8V V  
is also supported. Please contact Sony Memory Marketing Department for further information.  
DDQ  
HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.75V typical  
REF  
Register - Register (R-R) read protocol  
Late Write (LW) write protocol  
Full read/write coherency  
Byte Write capability  
Differential input clocks (K/K)  
Asynchronous output enable (G)  
Sleep (power down) mode via dedicated mode pin (ZZ)  
Programmable output driver impedance  
JTAG boundary scan (subset of IEEE standard 1149.1)  
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package  
32Mb LW R-R, rev 0.6  
1 / 22  
March 16, 2004  

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