Datasheet > CXK77K36R320GB-3

CXK77K36R320GB-3

更新时间： 2025-08-11 02:51:51

品牌	Logo	应用领域
索尼 - SONY		静态存储器
页数	文件大小	规格书
22页	177K
描述
32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)

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CXK77K36R320GB-3 数据手册

SONY

CXK77K36R320GB

3/33/4

32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)

Preliminary

Description

The CXK77K36R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words

by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer

onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro-

viding a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K

differential input clock.

During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

Sleep (power down) capability is provided via the ZZ input signal.

Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external

control resistor RQ between ZQ and V , the impedance of the output drivers can be precisely controlled.

333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of

IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

Cycle Time / Access Time

3.0ns / 1.6ns

-3

-33

-4

3.3ns / 1.6ns

4.0ns / 2.0ns

•

Single 2.5V power supply (V ): 2.5V ± 5%

Note: 1.8V V is also supported. Please contact Sony Memory Marketing Department for further information.

Dedicated output supply voltage (V

): 1.5V ± 0.1V

DDQ

Note: 1.8V V

is also supported. Please contact Sony Memory Marketing Department for further information.

DDQ

•

HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.75V typical

REF

Late Write (LW) write protocol

Full read/write coherency

Byte Write capability

Differential input clocks (K/K)

Asynchronous output enable (G)

Sleep (power down) mode via dedicated mode pin (ZZ)

Programmable output driver impedance

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

32Mb LW R-R, rev 0.6

1 / 22

March 16, 2004

12 3 4 5 6 7...22

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与CXK77K36R320GB-3相关器件

型号	品牌	获取价格	描述	数据表
CXK77K36R320GB-33	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
CXK77K36R320GB-4	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
CXK77L18162AGB	ETC	获取价格	MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-Hi
CXK77L18162GB	ETC	获取价格	MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (23 pages 312K Re
CXK77L18162GB-25	SONY	获取价格	DDR SRAM, 1MX18, 1.8ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77L18162GB-3	SONY	获取价格	DDR SRAM, 1MX18, 1.9ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77L18R160GB	ETC	获取价格	MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-Hi
CXK77L18R160GB-4	SONY	获取价格	Late-Write SRAM, 1MX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77N18B160GB-3	SONY	获取价格	Late-Write SRAM, 1MX18, 1.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77N18B160GB-33	SONY	获取价格	Late-Write SRAM, 1MX18, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

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