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CXA1102P PDF预览

CXA1102P

更新时间: 2024-09-16 22:40:23
品牌 Logo 应用领域
索尼 - SONY /
页数 文件大小 规格书
15页 475K
描述
DOLBY B TYPE NOISE REDUCTION SYSTEM

CXA1102P 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
风险等级:5.84商用集成电路类型:DOLBY NOISE REDUCTION IC
杜比水平规范:245 mV杜比类型:B
谐波失真:0.06%JESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.35 mm
信道数量:2功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
播放/录制模式:PLAYBACK AND RECORD电源:9 V
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Noise Suppression ICs最大压摆率:7.5 mA
最大供电电压 (Vsup):16 V最小供电电压 (Vsup):6.5 V
表面贴装:NO技术:BIPOLAR
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

CXA1102P 数据手册

 浏览型号CXA1102P的Datasheet PDF文件第9页浏览型号CXA1102P的Datasheet PDF文件第10页浏览型号CXA1102P的Datasheet PDF文件第11页浏览型号CXA1102P的Datasheet PDF文件第13页浏览型号CXA1102P的Datasheet PDF文件第14页浏览型号CXA1102P的Datasheet PDF文件第15页 
CXA1100/CXA1101/CXA1102/CXA1163  
4) MPX filter termination and C1 for Vcc/2 (Pin 4)  
The MPX (multiplex) filter termination method shown in Fig. a-3 allows saving the coupling capacitors  
between the buffer amplifiers and MPX filters. However, the channel to channel separation and REC to PB  
crosstalk of low frequency signals will be degraded by the termination resistor RT. For example, 5kof R1  
will degrade the channel to channel separation to 50dB. Better separation can be obtained by increasing  
the capacitance of C1 (Pin 4) to 220µF or 470µF.  
The allowable minimum value of C1 is 47µF, and 100µF is the standard recommended value. Larger values  
of C1 are generally desirable in order to improve the crosstalk and ripple rejection ratio.  
5) Application for dubbing cassette decks  
The CXA1100 series generates non decoded signal at the recoding output in the decode mode, and can  
simplify the structure of dubbing decks. See the SONY' Dolby B/C type IC (CX20187/CXA1097Q or  
CX20188/CXA1098Q) data sheet in detail.  
C11  
4.7µ  
Line  
Input  
Buffer  
MPX  
Filter  
13  
16  
15  
14  
RT  
RT  
CXA1100 Series  
1
2
3
4
Line  
Input  
Buffer  
MPX  
Filter  
C21  
4.7µ  
C1  
470µ  
Fig. a-3.  
Switchable Processor with Single Supply  
C3  
10µ  
REC/PB  
REC  
PB  
C14  
4.7µ  
R2  
PB IN  
LINE OUT  
REC OUT  
10k  
(–30dBm)  
C12  
R1  
(12  
%)  
C13 (10%)  
0.68µ  
1µ  
REC IN  
(–30dBm)  
43k  
C11  
1µ  
C15  
4.7µ  
13  
4
16  
15  
2
14  
3
12  
11  
10  
7
9
RT  
RT  
VCC  
C25  
4.7µ  
1
5
6
8
REC OUT  
(–10dBm)  
C1  
100µ  
C23 (10%)  
0.68µ  
REC IN  
(–30dBm)  
C2  
100µ  
LINE OUT  
C21  
1µ  
PB IN  
(–30dBm)  
C24  
4.7µ  
NR  
C22  
1µ  
ON/OFF  
OFF  
ON  
Note 1) Resistor and capacitor tolerances are ±10% and ±20% respectively unless otherwise specified.  
Note 2) When resistors RT are connected to Pin 4 for the MPX filter termination, increase the capacitances of  
C1 and C11 (C21) to 470µF and 4.7µF respectively.  
– 12 –  

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