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CS7054YN14 PDF预览

CS7054YN14

更新时间： 2024-02-05 18:44:03
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器MOSFET驱动器驱动程序和接口接口集成电路光电二极管控制器
页数 文件大小 规格书
12页 91K
描述
Low Side PWM FET Controller

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CS7054YN14 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：14
Reach Compliance Code：unknown风险等级：5.75
高边驱动器：YES接口集成电路类型：BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码：R-PDIP-T14长度：18.86 mm
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
标称输出峰值电流：0.4 A封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：COMMERCIAL
座面最大高度：4.69 mm最大供电电压：16 V
最小供电电压：8 V标称供电电压：12 V
表面贴装：NO温度等级：AUTOMOTIVE
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

CS7054YN14 数据手册

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CS7054  
APPLICATIONS INFORMATION  
THEORY OF OPERATION  
is compared to the oscillator voltage to produce the  
compensated duty cycle. The transfer is set up so that at V  
CC  
Oscillator  
= 14 V the duty will equal V  
divided by V  
. For  
CTL  
REG  
The IC sets up a constant frequency triangle wave at the  
lead whose frequency is determined by the external  
example at V = 14 V, V  
= 5.0 V and V  
= 2.5 V, the  
CC  
REG  
CTL  
C
OSC  
duty cycle would be 50% at the output. This would place a  
7.0 V average voltage across the load. If V then drops to  
components R  
and C  
by the following equation:  
OSC  
OSC  
CC  
10 V, the IC would change the duty cycle to 70% and hence  
keep the average load voltage at 7.0 V.  
0.83  
Frequency +  
R
  C  
OSC  
OSC  
The peak and valley of the triangle wave are proportional  
to V by the following:  
120  
100  
CC  
V
+ 0.2   V  
VALLEY  
CC  
CC  
V
CC  
= 8.0 V  
V
+ 0.8   V  
80  
60  
40  
20  
0
PEAK  
V
CC  
= 14 V  
This is required to make the voltage compensation  
function properly. In order to keep the frequency of the  
V
CC  
= 16 V  
oscillator constant the current that charges C  
must also  
OSC  
vary with supply. R  
sets up the current which charges  
OSC  
C
OSC  
. The voltage across R  
is 50% of V  
and  
OSC  
CC  
therefore:  
V
CC  
I
+ 0.5   
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
ROSC  
R
OSC  
CTL Voltage (% of V  
)
REG  
I
is multiplied by two (2) internally and transferred  
ROSC  
Figure 8. Voltage Compensation  
to the C  
lead. Therefore:  
OSC  
5.0 V Linear Regulator  
V
CC  
I
+"  
COSC  
There is a 5.0 V, 5.0 mA linear regulator available at the  
lead for external use. This voltage acts as a reference  
R
OSC  
V
REG  
The period of the oscillator is:  
for many internal and external functions. It has a drop out of  
approximately 1.5 V at room temperature and does not  
require an external capacitor for stability.  
V
* V  
PEAK  
I
VALLEY  
T + 2C  
 
OSC  
COSC  
The R  
and C  
components can be varied to create  
OSC  
OSC  
Current Sense and Timer  
frequencies over the range of 15 Hz to 25 kHz. With the  
suggested values of 105 kΩ and 390 pF for R and C  
The IC differentially monitors the load current on a cycle  
OSC  
OSC  
by cycle basis at the I  
and I  
leads. The  
SENSE+  
SENSE–  
respectively, the nominal frequency will be approximately  
20 kHz. I , at V = 14 V, will be 66.7 µA. I should  
differential voltage across these two leads is amplified  
internally and compared to the voltage at the I lead. The  
ROSC  
CC  
ROSC  
ADJ  
not change over a more than 2:1 ratio and therefore C  
should be changed to adjust the oscillator frequency.  
OSC  
gain, A , is set internally and externally by the following  
V
equation:  
Voltage Duty Cycle Conversion  
V
I(ADJ)  
* I  
SENSE*  
37000  
1000 ) R  
A
+
+
V
The IC translates an input voltage at the CTL lead into a  
duty cycle at the OUTPUT lead. The transfer function  
incorporates ON Semiconductor’s patented Voltage  
Compensation method to keep the average voltage and  
current across the load constant regardless of fluctuations in  
the supply voltage. The duty cycle is varied based upon the  
input voltage and supply voltage by the following equation:  
I
SENSE)  
CS  
The current limit (I ) is set by the external current sense  
LIM  
resistor (R  
) placed across the I  
terminals and the voltage at the I  
and I  
SENSE+ SENSE–  
SENSE  
lead.  
ADJ  
1000 ) R  
V
I(ADJ)  
SENSE  
CS  
I
+
 
LIM  
37000  
R
2.8   V  
The R resistors and C components form a differential  
low pass filter which filters out high frequency noise  
generated by the switching of the external MOSFET and the  
CTL  
CS  
CS  
Duty Cycle + 100%   
V
CC  
An internal DC voltage equal to:  
associated lead noise. R also forms an error term in the  
CS  
V
+ (1.683   V  
) ) V  
CTL  
gain of the I  
equation because the I  
and I  
SENSE+ SENSE–  
DC  
VALLEY  
LIM  
http://onsemi.com  
6
1...3456789...12

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