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CS5376

更新时间： 2024-09-25 23:43:47

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CS5376 Rev. A Errata\|Geophysical\|A/D Converters

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CS5376 数据手册

09/05/01

Errata: CS5376 Rev. A

(Reference CS5376 Data Sheet revision DS256PP1 dated Jan ‘01)

Introduction

The CS5376 is a low power multi-channel digital filter with integrated system peripherals.

It uses a coefficient programmable signal processing architecture to provide filtering for up

to four ∆−Σ modulators. Integrated peripherals simplify system design with a buffered

high speed serial data output port, a test bit stream generator suitable for driving a test

DAC, general purpose I/O pins for local hardware control, a secondary master mode SPI

port for serial peripherals, and a JTAG port for boundary scan testing. In addition, a clock

and synchronization block synchronizes the CS5376 to the host system, and a time break

controller generates timing reference information in the output data stream.

Contents

Erratum 1: “SDTKI signal timing into the SD port” on page 1

Erratum 2: “EEPROM configuration loader preamble” on page 5

1. SDTKI signal timing into the SD port

After filtering is completed, each 24-bit output sample is combined with an 8-bit status

word. This 32-bit data word is written to an 8-deep FIFO buffer and then transmitted to the

communications interface through the high speed serial data output port (SD port). The SD

port can operate in two configurations, a continuous output configuration where data is

output immediately when ready, or a requested output configuration where data is output

only when polled by the communications controller.

Continuous Output SD Port Configuration

The continuous output SD port configuration requires the SDTKI pin to receive continuous

rising edges. A simple method for generating rising edges on SDTKI is to connect it to a 4

MHz or slower system clock. Whenever output data is available from the decimation

engine, a rising edge on SDTKI initiates an SD port transaction.

Once an SD port transaction starts, the SDTKI signal must be gated off to ensure no rising

edges occur during the transaction. The easiest way to guarantee this is to gate the SDTKI

input signal with the SDRDY output signal using an AND gate. When an SD port

transaction starts, the SDRDY signal is driven low by the CS5376 which will gate off the

SDTKI input. When the SD port transaction is complete, the SDRDY signal automatically

returns high to re-enable the SDTKI input.

Cirrus Logic

ER256A1

AUG ‘01

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

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与CS5376相关器件

型号	品牌	获取价格	描述	数据表
CS5376A	CIRRUS	获取价格	LOW POWER MULTI CHANNEL DECIMATION FILTER
CS5376A_05	CIRRUS	获取价格	Low-power, Multi-channel Decimation Filter
CS5376A_08	CIRRUS	获取价格	Low-power, Multi-channel Decimation Filter
CS5376A-IQ	CIRRUS	获取价格	LOW POWER MULTI CHANNEL DECIMATION FILTER
CS5376A-IQZ	CIRRUS	获取价格	Low-power, Multi-channel Decimation Filter
CS5378	CIRRUS	获取价格	Low-power Single-channel Decimation Filter
CS5378_08	CIRRUS	获取价格	Low-power Single-channel Decimation Filter
CS5378-IS	CIRRUS	获取价格	Low-power Single-channel Decimation Filter
CS5378-ISZ	CIRRUS	获取价格	Low-power Single-channel Decimation Filter
CS5381	CIRRUS	获取价格	120 dB, 192 kHz, Multi-Bit Audio A/D Converter

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