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CS5378_08 PDF预览

CS5378_08

更新时间: 2024-09-26 06:49:27
品牌 Logo 应用领域
凌云 - CIRRUS /
页数 文件大小 规格书
88页 1068K
描述
Low-power Single-channel Decimation Filter

CS5378_08 数据手册

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CS5378  
Low-power Single-channel Decimation Filter  
Features  
Description  
The CS5378 is a multi-function digital filter utilizing a low-  
power signal processing architecture to achieve efficient  
filtering for a delta-sigma-type modulator. By combining  
the CS5378 with a CS3301A/02A differential amplifier  
and a CS5373A modulator + test DAC, a synchronous  
high-resolution, self-testing, single-channel measure-  
ment system can be designed quickly and easily.  
z Single-channel Digital Decimation Filter  
Œ Multiple On-chip FIR and IIR Coefficient Sets  
Œ Programmable Coefficients for Custom Filters  
Œ Synchronous Operation  
z Integrated PLL for Clock Generation  
Œ 1.024 MHz, 2.048 MHz, or 4.096 MHz Input  
Œ Standard Clock or Manchester Input  
z Selectable Output Word Rate  
Œ 4000, 2000, 1000, 500, 333, 250 SPS  
Œ 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS  
z Digital Gain and Offset Corrections  
z Test DAC Bit-stream Generator  
Œ Digital Sine Wave Output  
Digital filter coefficients for the CS5378 FIR and IIR filters  
are included on-chip for a simple setup, or they can be  
programmed for custom applications. Selectable digital  
filter decimation ratios produce output word rates from  
4000 SPS to 1 SPS, resulting in measurement band-  
widths ranging from 1600 Hz down to 400 mHz when  
using the on-chip coefficient sets.  
The CS5378 includes integrated peripherals to simplify  
system design: a low-jitter PLL for standard clock or  
Manchester inputs, offset and gain corrections, a test  
DAC bit stream generator, a time break controller, and  
eight general-purpose I/O pins.  
z Time Break Controller, General-purpose I/O  
z Microcontroller or EEPROM Configuration  
z Small-footprint, 28-pin SSOP Package  
z Low Power Consumption  
Œ 16 mW at 500 SPS OWR  
z Flexible Power Supplies  
Œ I/O Interface and PLL: 3.3 V or 5.0 V  
ORDERING INFORMATION  
See page 86.  
Œ Digital Logic Core: 2.5 V, 3.3 V or 5.0 V  
I
CLK  
PLL, Clock Generation  
MCLK  
Serial Interface  
RESET  
Reset, Synchronization  
Time Break Controller  
SYNC  
MSYNC  
TIMEB  
Decimation and  
Filtering Engine  
Test Bit Stream  
Controller  
TBSDATA  
GPIO7:BOOT  
GPIO6:PLL2  
GPIO5:PLL1  
GPIO4:PLL0  
GPIO3  
GPIO  
General Purpose I/O  
Modulator Data Interface  
GPIO2  
GPIO1  
GPIO0  
Copyright © Cirrus Logic, Inc. 2008  
SEP ‘08  
DS639F2  
http://www.cirrus.com  
(All Rights Reserved)  

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