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CS5376A_05

更新时间: 2024-09-26 04:12:43
品牌 Logo 应用领域
凌云 - CIRRUS /
页数 文件大小 规格书
108页 1296K
描述
Low-power, Multi-channel Decimation Filter

CS5376A_05 数据手册

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CS5376A  
Low-power, Multi-channel Decimation Filter  
Features  
Description  
The CS5376A is a multi-function digital filter utilizing a  
low-power signal processing architecture to achieve ef-  
ficient filtering for up to four ∆Σ modulators. By  
combining the CS5376A with CS3301/02 differential  
amplifiers, CS5371/72 ∆Σ modulators, and the  
CS4373A ∆Σ test DAC a synchronous, high-resolution,  
self-testing, multi-channel measurement system can be  
designed quickly and easily.  
z 1- to 4-channel Digital Decimation Filter  
Œ Multiple On-chip FIR and IIR Coefficient Sets  
Œ Programmable Coefficients for Custom Filters  
Œ Synchronous Operation  
z Selectable Output Word Rate  
Œ 4000, 2000, 1000, 500, 333, 250 SPS  
Œ 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS  
Digital filter coefficients for the CS5376A FIR and IIR fil-  
ters are included on-chip for a simple setup, or they can  
be programmed for custom applications. Selectable dig-  
ital filter decimation ratios produce output word rates  
from 4000 SPS to 1 SPS, resulting in measurement  
bandwidths ranging from 1600 Hz down to 400 mHz  
when using the on-chip coefficient sets.  
z Digital Gain and Offset Corrections  
z Test DAC Bit Stream Generator  
Œ Sine Wave or Impulse Output Mode  
z Time Break Controller, General Purpose I/O  
z Secondary SPI™ Port, Boundary Scan JTAG  
z Microcontroller or EEPROM Configuration  
z Small-footprint, 64-pin TQFP Package  
The CS5376A includes integrated peripherals to simplify  
system design: offset and gain corrections, a test DAC  
bit stream generator, a time-break controller, 12 gener-  
al-purpose I/O pins, a secondary SPI port, and a  
boundary scan JTAG port.  
z Low Power Consumption  
Œ 9 mW per Channel at 500 SPS  
z Flexible Power Supplies  
Œ I/O Interface: 3.3 V or 5.0 V  
ORDERING INFORMATION  
Œ Digital Logic Core: 3.0 V, 3.3 V or 5.0 V  
See page 107.  
I
CLK  
Clock and  
Synchronization  
SYNC  
M CLK  
M SYNC  
Serial Data Output Port  
SSI  
SCK1  
M ISO  
M OSI  
SPI 1  
Serial Peripheral Interface 1  
SINT  
TIM EB  
Tim e Break Controller  
TBSCLK  
TBSDATA  
Test Bit Stream Controller  
Decim ation and  
Filtering Engine  
GPIO11:EECS  
GPIO10  
GPIO9  
GPIO8  
GPIO7  
GPIO  
GPIO6  
GPIO5  
General Purpose I/O  
GPIO4:CS4  
GPIO3:CS3  
GPIO2:CS2  
GPIO1:CS1  
GPIO0:CS0  
SCK2  
SO  
JTAG  
SPI 2  
SI1  
M odulator Data  
Interface  
SI2  
Serial Peripheral Interface 2  
Interface  
SI3  
SI4  
Copyright © Cirrus Logic, Inc. 2005  
(All Rights Reserved)  
SEP ‘05  
DS612F3  
http://www.cirrus.com  

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