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CS5376A

更新时间: 2024-09-25 23:16:27
品牌 Logo 应用领域
凌云 - CIRRUS LTE
页数 文件大小 规格书
107页 1561K
描述
LOW POWER MULTI CHANNEL DECIMATION FILTER

CS5376A 数据手册

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CS5376A  
Low Power Multi-Channel Decimation Filter  
Features  
Description  
The CS5376A is a multi-function digital filter utilizing a  
low-power signal processing architecture to achieve effi-  
cient filtering for up to four ∆Σ modulators. By combining  
the CS5376A with CS3301/02 differential amplifiers,  
CS5371/72 ∆Σ modulators, and the CS4373 ∆Σ test  
DAC a synchronous high resolution multi-channel mea-  
surement system can be designed quickly and easily.  
1 to 4 Channel Digital Decimation Filter  
Multiple On-Chip FIR and IIR Coefficient Sets  
Programmable Coefficients for Custom Filters  
Synchronous Operation  
Selectable Output Word Rate  
4000, 2000, 1000, 500, 333, 250 SPS  
200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS  
Digital Gain and Offset Corrections  
Test DAC Bit Stream Generator  
Sine Wave or Impulse Output Mode  
Time Break Controller, General Purpose I/O  
Secondary SPI Port, Boundary Scan JTAG  
Microcontroller or EEPROM Configuration  
Small Footprint 64-pin TQFP Package  
Low Power Consumption  
Digital filter coefficients for the CS5376A FIR and IIR fil-  
ters are included on-chip for a simple setup, or they can  
be programmed for custom applications. Selectable dig-  
ital filter decimation ratios produce output word rates  
from 4000 SPS to 1 SPS, resulting in measurement  
bandwidths ranging from 1600 Hz down to 400 mHz  
when using the on-chip coefficient sets.  
The CS5376A includes integrated peripherals to simplify  
system design: offset and gain corrections, a test DAC  
bit stream generator, a time break controller, 12 general  
purpose I/O pins, a secondary SPI port, and a boundary  
scan JTAG port.  
9 mW per Channel at 500 SPS  
Flexible Power Supplies  
I/O Interface: 3.3 V or 5.0 V  
Digital Logic Core: 3.0 V, 3.3 V or 5.0 V  
ORDERING INFORMATION  
o
CS5376A-IQ  
-40 to +85 C  
64-pin TQFP  
I
CLK  
Clock and  
Synchronization  
SYN C  
M CLK  
Serial Data O utput Port  
M SYNC  
SSI  
SCK 1  
M ISO  
M OSI  
SPI 1  
Serial Peripheral Interface 1  
SINT  
TIM EB  
Tim e Break Controller  
TB SC LK  
Test Bit Stream Controller  
TB SD ATA  
Decim ation and  
Filtering Engine  
G PIO 11:EECS  
G PIO 10  
G PIO 9  
G PIO 8  
G PIO 7  
G PIO  
G PIO 6  
G PIO 5  
General Purpose I/O  
G PIO 4:CS4  
G PIO 3:CS3  
G PIO 2:CS2  
G PIO 1:CS1  
G PIO 0:CS0  
SCK 2  
SO  
JTAG  
SPI 2  
SI1  
Modulator Data  
Interface  
SI2  
Serial Peripheral Interface 2  
Interface  
SI3  
SI4  
Copyright Cirrus Logic, Inc. 2004  
(All Rights Reserved)  
FEB ‘04  
DS612F1  
http://www.cirrus.com  
1

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