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CPC7593ZCTR

更新时间: 2024-11-25 06:48:27
品牌 Logo 应用领域
CLARE 电信集成电路光电二极管
页数 文件大小 规格书
24页 691K
描述
Line Card Access Switch

CPC7593ZCTR 数据手册

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CPC7593  
Line Card Access Switch  
Features  
Description  
TTL logic level inputs for 3.3V logic interfaces  
Smart logic for power up / hot plug state control  
Improved switch dv/dt immunity of 500 V/μs  
Small 20-pin or 28-pin SOIC or 28-pin DFN package  
DFN version provides 65% PCB area reduction over  
The CPC7593 is a member of Clare’s next generation  
Line Card Access Switch (LCAS) family. This  
monolithic 10-pole line card access switch is available  
in a 20 or 28 pin SOIC or a 28 pin DFN package. It  
provides the necessary functions to replace three  
2-Form-C electromechanical relays on analog line  
cards or combined voice and data line cards found in  
central office, access, and PBX equipment. The  
device contains solid state switches for tip and ring line  
break, ringing injection and test access. The CPC7593  
requires only a +5 V supply and provides stable start  
up conditioning during system power up and for hot  
plug insertion applications. Once active, the inputs  
respond to traditional TTL logic levels enabling the  
CPC7593 to be used with 3.3V only logic.  
th  
4 generation EMRs  
Monolithic IC reliability  
Low, matched, R  
Eliminates the need for zero-cross switching  
Flexible switch timing for transition from ringing  
mode to talk mode.  
ON  
Clean, bounce-free switching  
SLIC tertiary protection via integrated current  
limiting, voltage clamping and thermal shutdown  
5 V operation with power consumption < 10.5 mW  
Intelligent battery monitor  
Ordering Information  
Logic-level inputs, no external drive circuitry required  
CPC7593 part numbers are specified as shown here:  
Applications  
Standard voice linecards  
Integrated Voice and Data (IVD) linecards  
Central office (CO)  
B - 28-pin SOIC delivered 29/Tube, 1000/Reel  
M - 28-pin DFN delivered 33/Tube, 1000/Reel  
Z - 20-pin SOIC delivered 40/Tube, 1000/Reel  
Digital Loop Carrier (DLC)  
PBX Systems  
Digitally Added Main Line (DAML)  
Hybrid Fiber Coax (HFC)  
Fiber in the Loop (FITL)  
Pair Gain System  
CPC7593 x x xx  
TR - Add for Tape & Reel Version  
A - With Protection SCR  
B - Without Protection SCR  
C - With Protection SCR and with Extra Logic State  
D - Without Protection SCR and with Extra Logic State  
Channel Banks  
RoHS  
2002/95/EC  
Pb  
e3  
Figure 1. CPC7593 Block Diagram  
(TCHANTEST  
)
TTESTin  
+5 Vdc  
12 VDD  
(TDROPTEST  
)
TTESTout  
TRINGING  
10  
8
5
SW7  
X
CPC7593  
XSW5  
SW3  
Tip  
X
X
SW9  
6 TBAT  
TLINE  
7
X
SW1  
Secondary  
Protection  
SLIC  
Ring  
SW2  
X
23 RBAT  
17  
RLINE  
22  
INTESTin  
L
A
T
C
H
SW10  
SW4  
X
SW6  
X
X
SCR  
Trip  
Circuit  
16  
Switch  
Control  
Logic  
INRINGING  
INTESTout  
VREF  
15  
X
SW8  
18  
LATCH  
19  
20  
24  
1
FGND  
14 13  
DGND  
RRINGING  
28  
RTESTout (RDROPTEST  
)
TSD  
300Ω (min.)  
VBAT  
RINGING  
VBAT  
NOTE 1: Pin assignments are for the 28 pin package.  
R
TESTin (RCHANTEST)  
NOTE 2: Block diagram shown with the optional protection SCR.  
DS-CPC7593 - R04  
www.clare.com  
1

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