Datasheet > COREPCI-AN

COREPCI-AN

更新时间： 2024-11-05 06:48:27

品牌	Logo	应用领域
ACTEL		PC
页数	文件大小	规格书
42页	358K
描述
CorePCI v5.41

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中文翻译

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数据手册

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COREPCI-AN 数据手册

CorePCI v5.41

Synthesis and Simulation Support

Product Summary

•

Synthesis: Exemplar^TM, Synopsys^®DC / FPGA Compiler^TM,

and Synplicity^®

Intended Use

•

Simulation: Vital-Compliant VHDL Simulators and

OVI- Compliant Verilog Simulators

•

Most Flexible High-Performance PCI Offering

–

Target, Master, and Master/Target, which

includes Target+DMA and Target+Master

functions

Macro Verification and Compliance

•

Actel-Developed Testbench

–

33 MHz or 66 MHz Performance

32-Bit or 64-Bit PCI Bus Widths

Hardware Tested

I/O Drive Compliant in Targeted Devices

Compliant with the PCI 2.3 Specification

Memory, I/O, and Configuration Support

•

Backend Support for Synchronous DRAM, SRAM,

and I/O Subsystems

Version

Key Features

This datasheet defines the functionality of Version 5.41

for CorePCI.

•

Two User-Configurable Base Address Registers for

Target Functions

Contents

•

Interrupt Capability

Built-in DMA Controller in all Master Functions

Flexible Backend Data Flow Control

General Description ................................................... 2

CorePCI Device Requirements ................................... 3

Utilization Statistics ................................................... 5

CorePCI IP Functional Block Diagram ....................... 6

Data Transactions ....................................................... 6

I/O Signal Descriptions ............................................... 6

CorePCI Target Function .......................................... 12

CorePCI Master Function ......................................... 17

Master Register Access ............................................. 19

System Timing .......................................................... 22

PCI Target Transactions ............................................ 22

PCI Master Transactions ........................................... 35

Backend Control of DMA Activity ........................... 38

Ordering Information .............................................. 40

List of Changes ......................................................... 41

Datasheet Categories ............................................... 41

Hot-Swap Extended Capabilities Support for

Compact PCI

Data Transfer Rates

•

Fully Compliant Zero-Wait-State Burst (32-Bit or

64-Bit Transfer Each Cycle)

•

Optional Paced Burst (Wait States Inserted

Between Transfers)

Supported Families

•

ProASIC3/E

ProASIC^{PLUS 1}

Axcelerator

RTAX-S

SX-A

RTSX-S¹

Design Source Provided

•

VHDL and Verilog-HDL Design Source

•

Actel-Developed Testbench

October 2004

v4.0

12 3 4 5 6 7...42

中文翻译

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与COREPCI-AN相关器件

型号	品牌	获取价格	描述	数据表
COREPCI-AR	ACTEL	获取价格	CorePCI v5.41
COREPCI-EV	ACTEL	获取价格	CorePCI v5.41
COREPCI-SN	ACTEL	获取价格	CorePCI v5.41
COREPCI-SR	ACTEL	获取价格	CorePCI v5.41
COREPCI-UR	ACTEL	获取价格	CorePCI v5.41
COREPCI-XX	ACTEL	获取价格	CorePCI v5.41
CORESDLC-AN	ACTEL	获取价格	CoreSDLC
CORESDLC-AR	ACTEL	获取价格	CoreSDLC
CORESDLC-EV	ACTEL	获取价格	CoreSDLC
CORESDLC-SN	ACTEL	获取价格	CoreSDLC

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