Datasheet > COREU1PHY-XX

COREU1PHY-XX

更新时间： 2024-11-09 06:48:27

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
8页	92K
描述
CoreU1PHY - UTOPIA Level 1 PHY Interface

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COREU1PHY-XX 数据手册

CoreU1PHY – UTOPIA Level 1 PHY Interface

Libero IDE and Industry Standard Synthesis and

Simulation Tools

RTL Version

Product Summary

•

Intended Use

–

VHDL Source Code

•

Standard UTOPIA Level 1 PHY Interface to any

ATM Link-Layer Device

Core Synthesis and Simulation Scripts

Actel-Developed

Testbench

(VHDL)

Fully

Supported by Industry-Standard Simulation Tools

Key Features

Design Tools Support

•

Standard 8-Bit, 25 MHz UTOPIA Level 1 PHY

Interface Complies with the ATM Forum UTOPIA

•

Simulation: VITAL Compliant VHDL and OVI

Compliant Verilog Simulators

Specification, Level

0017.000)

Version 2.01 (af-phy-

•

Synthesis: LeonardoSpectrum^®, Synplify^®, Design

•

Separate TX and RX Clocks and Interface Pins

Compiler^®, FPGA Compiler^TM, and FPGA Express^TM

Supports Cell-Level Handshake for 53- or 54-byte

ATM Cells with Automatic Add/Drop of UDF2 Field

in the ATM Header in 53-byte Mode

Contents

•

16-Bit (54-byte) User Interfaces Can be Used

Directly or Bolt-Up to One of Actel's ATM Cell

Buffer Blocks: ATMBUFx

General Description ................................................... 1

Device Requirements ................................................. 2

UTOPIA Interface ....................................................... 2

User Interface ............................................................. 4

Ordering Information ................................................ 6

List of Changes ........................................................... 7

Datasheet Categories ................................................. 7

Supported Families

•

Fusion

ProASIC3/E

ProASIC^PLUS®

Axcelerator^®

Core Deliverables

General Description

•

Netlist Version

CoreU1PHY is a UTOPIA Level 1 PHY interface core that

connects directly to any ATM link-layer (master) device

and user logic (or optional ATM cell buffer blocks) to

provide an interface between the link-layer device and a

non-standard physical layer device (Figure 1).

–

Compiled RTL Simulation Model Fully

Supported in Actel Libero^®Integrated Design

Environment (IDE)

–

Structural VHDL and Verilog Netlists (with and

without I/O Pads) Compatible with Actel’s

Utopia

CoreATMBUF3

Level 1

Link-Layer

Device

Other

Device

User

Logic

CoreU1PHY

CoreATMBUF3

Figure 1 • Block Diagram

December 2005

v4.0

12 3 4 5 6 7 8

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