Datasheet > CM2006

CM2006

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CALMIRCO		显示器
页数	文件大小	规格书
6页	137K
描述
VGA Port Companion Circuit For Monitors

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中文翻译

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数据手册

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CM2006 数据手册

PRELIMINARY

CM2006

VGA Port Companion Circuit For Monitors

Product Description

Features

•

Includes ESD protection, level-shifting, buffering

and sync impedance matching

VESA VSIS Version 1 Revision 2 Compatible Inter-

face

Supports Optional NAVI Signalling requirements

7 channels of ESD protection for all VGA port con-

nector pins meeting IEC-61000-4-2 Level 4 ESD

requirements ( 8kV contact discharge)

Very low loading capacitance from ESD protection

diodes on VIDEO lines, 3pF maximum

Schmitt triggered input buffers for HSYNC and

VSYNC lines

The CM2006 connects between the VGA or DVI-I port

connector and the internal analog or digital flat panel

controller logic. The CM2006 incorporates ESD protec-

tion for all signals, level shifting for the DDC signals

and buffering for the SYNC signals. ESD protection for

the video, DDC and SYNC lines is implemented with

low-capacitance current steering diodes.

•

All connector interface pins are designed to safely han-

dle the high current spikes specified by IEC-61000-4-2

Level 4 ( 8kV contact discharge). The ESD protection

for the DDC, SYNC and VIDEO signal pins is designed

to prevent "back current" when the device is powered

down while connected to a video source that is pow-

ered up.

•

Bi-directional level shifting N-channel FETs pro-

vided for DDC_CLK & DDC_DATA channels

Backdrive protection on all lines

•

Compact 16-lead QSOP package

Separate positive supply rails are provided for the

VIDEO / SYNC signals and DDC signals to facilitate

interfacing with low voltage video controller ICs and

microcontrollers to provide design flexibility in multi-

supply-voltage environments.

Applications

•

VGA and DVI-I ports in:

- Monitors

Two Schmitt-Triggered non-inverting buffers redrive

and condition the HSYNC and VSYNC signals from the

video Connector (SYNC1, SYNC2). These buffers

accept VESA VSIS compliant TTL input signals and

convert them to CMOS output levels that swing

- Set Top Boxes

between Ground and V

(cont’d next page)

Simplified Electrical Schematic

BYP

CC_DDC

DDC_OUT1

DDC_OUT2

VIDEO_1

VIDEO_2

VIDEO_3

R_T

GND

SYNC_OUT2

SYNC_OUT1

GND

DDC_IN1

DDC_IN2

ENABLE

SYNC_IN1

SYNC_IN2

02/21/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

●

Tel: 408.263.3214

●

Fax: 408.263.7846

●

www.cmd.com

12 3 4 5 6

中文翻译

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