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CLC5523I PDF预览

CLC5523I

更新时间: 2024-02-07 05:52:55
品牌 Logo 应用领域
美国国家半导体 - NSC 放大器
页数 文件大小 规格书
12页 157K
描述
Low-Power, Variable Gain Amplifier

CLC5523I 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:unknown风险等级:5.65
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:R-PDIP-T8
JESD-609代码:e0长度:9.817 mm
湿度敏感等级:NOT SPECIFIED标称负供电电压 (Vsup):-5 V
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:5.08 mm
标称供电电压 (Vsup):5 V表面贴装:NO
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

CLC5523I 数据手册

 浏览型号CLC5523I的Datasheet PDF文件第4页浏览型号CLC5523I的Datasheet PDF文件第5页浏览型号CLC5523I的Datasheet PDF文件第6页浏览型号CLC5523I的Datasheet PDF文件第8页浏览型号CLC5523I的Datasheet PDF文件第9页浏览型号CLC5523I的Datasheet PDF文件第10页 
Minimizing Parasitic Effects on  
Small Signal Bandwidth  
Long traces between CLC5523 and 0.1mF  
bypass capacitors  
The best way to minimize parasitic effects is to use the  
small outline package and surface mount components.  
For designs utilizing through-hole components,  
specifically axial resistors, resistor self-capacitance  
should be considered. Example: the average magnitude  
of parasitic capacitance of RN55D 1% metal film  
resistors is about 0.15pF with variations of as much as  
0.1pF between lots. Given the CLC5523’s extended  
bandwidth, these small parasitic reactance variations can  
cause measurable frequency response variations in the  
highest octave. We therefore recommend the use  
of surface mount resistors to minimize these parasitic  
reactance effects. If an axial component is preferred, we  
recommend PRP8351 resistors which are available from  
Precision Resistive Products, Inc., Highway 61 South,  
Mediapolis, Iowa.  
Keep these traces less than 0.2 inches (5mm)  
For the devices in the PDIP package, an  
additional 1000pF monolithic capacitor should be  
placed less than 0.1” (3mm) from the pin  
Extra capacitance between the R pin and  
g
ground (C )  
G
See the Printed Circuit Board Layout sub-section  
below for suggestions on reducing C  
G
Increase R if peaking is still observed after  
f
reducing C  
G
Non-inverting input pin connected directly to  
ground  
Place a 50 to 200W resistor between the non-  
inverting pin and ground  
Adjusting Offsets and DC Level Shifting  
Offsets can be broken into two parts: an input-referred term  
and an output-referred term. These errors can be trimmed  
Small Signal Response at Low A  
vmax  
When the maximum gain, as set by R and R , is greater  
using the circuit in Figure 4. First set V to 0V and adjust  
g
f
G
than or equal to A  
= 10, little or no peaking should be  
the trim pot R4 to null the offset voltage at the output. This  
vmax  
observed in the amplifier response. When the gain range  
is set to less than A = 10, some peaking may  
will eliminate the output stage offsets. Next set V to 2V  
and adjust the trim pot R1 to null the offset voltage at the  
output. This will eliminate the input stage offsets.  
G
vmax  
be observed at higher frequencies. At gain ranges of  
2 ² A ² 10 peaking can be minimized by increasing  
vmax  
R . At gain ranges of A  
approximately 6dB in the upper octave.  
< 2 peaking reaches  
f
vmax  
VG  
1
Vin  
2
3
If peaking is observed with the recommended R resistor,  
and a small increase in the R resistor does not solve the  
problem, then investigate the possible causes and  
remedies listed below.  
f
Vo  
6
CLC5523  
f
7
+5V  
Rf  
R2  
4
+5V  
10k  
Rg  
R1  
10k  
R3  
10k  
25W  
Capacitance across R  
f
R4  
10k  
0.1mF  
Do not place a capacitor across R  
f
-5V  
Keep traces connecting R separated and as  
0.1mF  
f
short as possible  
-5V  
Capacitive Loads  
Place a small resistor (20-50W) between the  
Figure 4: Offset Adjust Circuit  
output and C  
L
Long traces and/or lead lengths between R  
and the CLC5523  
f
Keep these traces as short as possible  
7
http://www.national.com  

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