CDP1872C,
CDP1874C, CDP1875C
March 1997
High-Speed 8-Bit Input and Output Ports
Features
Description
• Parallel 8-Bit Input/Output Register with Buffered Out- The CDP1872C, CDP1874C and CDP1875C devices are
puts
high-speed 8-bit parallel input and output ports designed for
use in the CDP1800 microprocessor system and for general
use in other microprocessor systems. The CDP1872C and
CDP1874C are 8-bit input ports; the CDP1875C is an 8-bit
output port.
• High-Speed Data-In to Data-Out 85ns (Max) at VDD = 5V
• Flexible Applications In Microprocessor Systems as
Buffers and Latches
These devices have flexible capabilities as buffers and data
latches and are reset by CLR input when the data strobe is
not active.
• High Order Address-Latch Capability in CDP1800-
Series Microprocessor Systems
• Output Sink Current = 5mA (Min) at VDD = 5V
• Three-State Output - CDP1872C and CDP1874C
The CDP1872C and CDP1874C are functionally identical
except for device selects.The CDP1872C has one active low
and one active high select; the CDP1874C has two active
high device selects. These devices also feature Three-state
outputs when deselected. Data is strobed into the register on
the leading edge of the CLOCK and latched on the trailing
edge of the CLOCK.
Ordering Information
PART
NUMBER
PKG.
NO.
TEMP. RANGE
PACKAGE
o
o
The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.
CDP1872CE
CDP1874CE
CDP1875CE
-40 C to +85 C PDIP
E22.4
E22.4
E22.4
o
o
-40 C to +85 C PDIP
o
o
-40 C to +85 C PDIP
Pinouts
CDP1874C INPUT PORT
(PDIP)
CDP1875C OUTPUT PORT
(PDIP)
CDP1872C INPUT PORT
(PDIP)
TOP VIEW
TOP VIEW
TOP VIEW
1
2
22
1
2
22
21
20
19
18
17
16
15
14
13
12
1
22
21
20
19
18
17
16
15
14
13
12
VDD
DI7
D07
DI6
D06
DI5
D05
DI4
D04
VDD
DI7
D07
DI6
D06
DI5
D05
DI4
D04
VDD
DI7
D07
DI6
D06
DI5
D05
DI4
D04
CS1
CS1
CS1
21
20
19
18
17
16
15
14
13
12
2
DI0
DI0
DI0
3
3
3
DO0
DO0
DO0
4
4
4
DI1
D01
DI1
D01
DI2
DI1
5
5
5
D01
6
6
7
6
DI2
D02
DI2
7
7
D02
D02
DI3
8
8
8
DI3
DI3
9
9
9
D03
D03
D03
CS3
VSS
10
11
10
11
10
11
CLOCK
VSS
CLOCK
VSS
CLR
CS2
CLR
CS2
CLR
CS2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1255.2
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