CDP1877,
CDP1877C
March 1997
Programmable Interrupt Controller (PIC)
Features
Description
The CDP1877 and CDP1877C are programmable 8-level interrupt control-
lers designed for use in CDP1800 series microprocessor systems. They
provide added versatility by extending the number of permissible interrupts
from 1 to N in increments of 8.
• Compatible with CDP1800 Series
• Programmable Long Branch Vector Address and
Vector Interval
When a high to low transition occurs on any of the PIC interrupt lines (IR0 to
IR7), it will be latched and, unless the request is masked, it will cause the
INTERRUPT line on the PIC and consequently the INTERRUPT input on
the CPU to go low.
• 8 Levels of Interrupt Per Chip
• Easily Expandable
• Latched Interrupt Requests
• Hard Wired Interrupt Priorities
• Memory Mapped
The CPU accesses the PIC by having interrupt vector register R(1) loaded
with the memory address of the PIC. After the interrupt S3 cycle, this regis-
ter value will appear at the CPU address bus, causing the CPU to fetch an
instruction from the PIC. This fetch cycle clears the interrupt request latch
bit to accept a new high-to-low transition, and also causes the PIC to issue a
long branch instruction (CO) followed by the preprogrammed vector address
written into the PIC’s address registers, causing the CPU to branch to the
address corresponding to the highest priority active interrupt request.
• Multiple Chip Select Inputs to Minimize Address
Space Requirements
If no other unmasked interrupts are pending, the INTERRUPT output of the
PIC will return high. When an interrupt is requested on a masked interrupt
line, it will be latched but it will not cause the PIC INTERRUPT output to go
low. All pending interrupts, masked and unmasked, will be indicated by a “1”
in the corresponding bit of the status register. Reading of the status register
will clear all pending interrupt request latches.
Ordering Information
TEMP.
PKG.
NO.
PACKAGE RANGE
5V
10V
o
PDIP
-40 C to CDP1877CE CDP1877E E28.6
o
+85 C
Several PICs can be cascaded together by connecting the INTERRUPT out-
put of one chip to the CASCADE input of another. Each cascaded PIC pro-
vides 8 additional interrupt levels to the system. The number of units
cascadable depends on the amount of memory space and the extent of the
address decoding in the system.
Interrupts are prioritized in descending order; IR7 has the highest and IR0
has the lowest priority.
The CDP1877 and CDP1877C are functionally identical. They differ in that
the CDP1877 has a recommended operating voltage range of 4V to 10.5V,
and the CDP1877C has a recommended operating voltage range of 4V to
6.5V.
Pinout
Programming Model
PROGRAMMABLE INTERRUPT CONTROLLER (PIC)
CDP1877, CDP1877C (PDIP)
TOP VIEW
BUS 7
BUS 0
CASCADE
IR7
1
2
3
4
5
6
7
8
9
28 VDD
PAGE REGISTER
A12 A11
WRITE
ONLY
27 BUS 7
26 BUS 6
25 BUS 5
24 BUS 4
23 BUS 3
22 BUS 2
21 BUS 1
A15
A14
B6
A13
B5
A10
B2
A9
B1
M1
S1
P1
A8
IR6
BUS 7
BUS 0
IR5
CONTROL REGISTER
B4 B3
WRITE
ONLY
IR4
B7
B0
IR3
BUS 7
BUS 0
IR2
MASK REGISTER
M4 M3
WRITE
ONLY
IR1
M7
M6
S6
M5
S5
M2
S2
M0
IR0
20
BUS 0
BUS 7
BUS 0
TPA 10
TPB 11
MWR 12
MRD 13
VSS 14
19 CS/Ax
18 CS/Ay
17 CS
STATUS REGISTER
S4 S3
READ
ONLY
S7
S0
BUS 7
BUS 0
16 CS
POLLING REGISTER
P4 P3
READ
ONLY
15 INT
P7
P6
P5
P2
P0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1319.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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