Datasheet > CDP1857

CDP1857

更新时间： 2024-11-19 22:48:47

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
4页	28K
描述
4-Bit Bus Buffer/Separator

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CDP1857 数据手册

CDP1857C

4-Bit Bus Buffer/Separator

March 1997

Features

Description

The CDP1857C is a 4-bit CMOS non-inverting bus separator

designed for use in CDP1800-series microprocessor systems. It can

be controlled directly by a 1800-series microprocessor without the

use of additional components.

• Provides Easy Connection of I/O to CDP1800-Series

Microprocessor Data Bus

• Non-Inverting Fully Buffered Data Transfer

Ordering Information

PART

The CDP1857 is designed for use as a bus buffer or separator

between the 1800-series microprocessor data bus and I/O devices.

It provides a chip-select (CS) input signal which, when high (1),

enables the bus-separator three-state output drivers. The direction

of data ﬂow, when enabled, is controlled by the MRD input signal.

NUMBER

CDP1857CE

CDP1857CD

TEMP. RANGE

PACKAGE

PKG. NO.

E16.3

-40 C to +85 C PDIP

In the CDP1857, when MRD = 1, it enables the three-state bus drivers

(DB0-DB3) and transfers data from the DATA-IN lines onto the data

bus. When MRD = 0, it disables the three-state bus drivers (DB0-

DB3) and enables the three-state data output drivers (DO0-DO3),

thus, transferring data from the data bus to the DATA-OUT terminals.

-40 C to +85 C SBDIP

D16.3

TABLE 1. CDP1857 FUNCTION FOR I/O BUS SEPARATOR

OPERATION

The CDP1857 can be used as a bidirectional bus buffer by connecting

the corresponding DI and DO terminals (Figure 1). The MRD output

signal from the 1800-series microprocessor has the correct polarity to

control the CDP1857 when it is used as I/O bus buffer/separator.

Therefore, the 1800-series microprocessor MRD signal can be

connected directly to the MRD input of CDP1857. See Function Table

1 for use of the CDP1857 as an I/O bus buffer/separator.

DATA BUS OUT

DB0-DB3

DATA OUT

DO0-DO3

MRD

High Impedance

Data In

High Impedance

Data Bus

High Impedance

The CDP1857C is supplied in 16-lead hermetic, dual-in-line ceramic

packages (D sufﬁx), and in 16-lead plastic packages (E sufﬁx).

Pinout

Functional Diagram For CDP1857

16 LEAD DIP

TOP VIEW

DI0

DB0

DI0

DI1

16 V

DO0

15 CS

DO0

DO1

DO2

DO3

DI2

14 DB0

13 DB1

12 DB2

11 DB3

10 MRD

DI1

DB1

DO1

DI2

DI3

DB2

DO2

DI3

DB3

DO3

16 = V

8 = V

MRD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 1192.2

4-62

12 3 4

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CDP1857C_1	INTERSIL	获取价格	4-Bit Bus Buffer/Separator
CDP1857CD	INTERSIL	获取价格	4-Bit Bus Buffer/Separator
CDP1857CD3	RENESAS	获取价格	CDP1857CD3
CDP1857CDX	RENESAS	获取价格	CDP1857CDX
CDP1857CE	INTERSIL	获取价格	4-Bit Bus Buffer/Separator
CDP1857CEX	RENESAS	获取价格	CDP1857CEX
CDP1857D	RENESAS	获取价格	CDP1857D
CDP1857E	ETC	获取价格	Peripheral IC
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