Datasheet > CDK8307BITQ80

CDK8307BITQ80

更新时间： 2024-02-27 16:25:41

品牌	Logo	应用领域
CADEKA		/
页数	文件大小	规格书
29页	1423K
描述
12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS

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中文翻译

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CDK8307BITQ80 数据手册

PRELIMINARY Data Sheet

Amplify the Human Experience

CDK8307

12/13-bit, 20/40/50/65MSPS, Eight Channel,

Ultra Low Power ADC with LVDS

F E A T U R E S

General Description

nꢀ

20/40/50/65MSPS maximum sampling rate

The CDK8307 is a high performance low power octal analog-to-digital

converter (ADC). The ADC employs internal reference circuitry, a serial control

interface and serial LVDS output data, and is based on a proprietary structure.

nꢀ

Low Power Dissipation

– 22mW/channel at 20MSPS

– 34mW/channel at 40MSPS

– 40mW/channel at 50MSPS

– 50mW/channel at 65MSPS

72.2dB SNR at 8MHz F_IN

An integrated PLL multiplies the input sampling clock by a factor of 12 or 14,

according to the LVDS output setting. The multiplied clock is used for data

serialization and data output. Data and frame synchronization output clocks are

supplied for data capture at the receiver.

nꢀ

0.5μs startup time from Sleep

15μs startup time from Power Down

Various modes and conﬁguration settings can be applied to the ADC through

the serial control interface (SPI). Each channel can be powered down inde-

pendently and data format can be selected through this interface. A full chip

idle mode can be set by a single external pin. Register settings determines the

exact function of this external pin.

Internal reference circuitry requires no

external components

nꢀ

Internal offset correction

Reduced power dissipation modes available

– 32mW/channel at 50MSPS

– 71.5dB SNR at 8MHz F_IN

Coarse and ﬁne gain control

1.8V supply voltage

The CDK8307 is designed to easily interface with ﬁeld-programmable gate

arrays (FPGAs) from several vendors.

nꢀ

The very low startup times of the CDK8307 allow signiﬁcant power reduction

in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when

the receive path is idle.

Serial LVDS output

– 12- and 14-bit output available

Package alternatives

nꢀ

Block Diagram

– TQFP-80

– QFN-64

A P P L I C A T I O N S

FCLKP

nꢀ

Medical Imaging

Serial Control

Interface

Clock

Input

FCLKN

LCLKP

LCLKN

PLL

LVDS

nꢀ

Wireless Infrastructure

nꢀ

Test and Measurement

IP1

IN1

D1N

D1P

Digital

Gain

ADC

nꢀ

Instrumentation

IP2

IN2

D2N

D2P

Digital

Gain

ADC

LVDS

•

IP8

IN8

D8N

D8P

Digital

Gain

ADC

LVDS

www.cadeka.com

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中文翻译

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与CDK8307BITQ80相关器件

型号	品牌	获取价格	描述	数据表
CDK8307CILP64	CADEKA	获取价格	12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8307CILP64B2	CADEKA	获取价格	12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8307CITQ80	CADEKA	获取价格	12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8307DILP64	CADEKA	获取价格	12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8307DILP64B2	CADEKA	获取价格	12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8307DITQ80	CADEKA	获取价格	12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8307EILP64	CADEKA	获取价格	12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8307EITQ80	CADEKA	获取价格	12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS
CDK8920A	CIRRUS	获取价格	CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
CDL13005	RECTRON	获取价格	NPN PLASTIC POWER TRANSISTOR

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