Data Sheet
Amplify the Human Experience
CDK8307
12/13-bit, 20/40/50/65/80MSPS, Eight Channel,
Ultra Low Power ADC with LVDS
F E A T U R E S
General Description
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20/40/50/65/80MSPS max sampling rate
The CDK8307 is a high performance low power octal analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a serial control
interface and serial LVDS output data, and is based on a proprietary structure.
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Low Power Dissipation
– 23mW/channel at 20MSPS
– 35mW/channel at 40MSPS
– 41mW/channel at 50MSPS
– 51mW/channel at 65MSPS
– 59mW/channel at 80MSPS
72.2dB SNR at 8MHz FIN
An integrated PLL multiplies the input sampling clock by a factor of 12 or 14,
according to the LVDS output setting. The multiplied clock is used for data
serialization and data output. Data and frame synchronization output clocks are
supplied for data capture at the receiver.
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Various modes and configuration settings can be applied to the ADC through
the serial control interface (SPI). Each channel can be powered down inde-
pendently and data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register settings determines the
exact function of this external pin.
0.5μs startup time from Sleep
15μs startup time from Power Down
Internal reference circuitry requires no
external components
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Internal offset correction
Reduced power dissipation modes available
– 34mW/channel at 50MSPS
– 71.5dB SNR at 8MHz FIN
Coarse and fine gain control
1.8V supply voltage
The CDK8307 is designed to easily interface with field-programmable gate
arrays (FPGAs) from several vendors.
The very low startup times of the CDK8307 allow significant power reduction
in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when
the receive path is idle.
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Serial LVDS output
– 12- and 14-bit output available
Package alternatives
Block Diagram
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– TQFP-80
– QFN-64
FCLKP
A P P L I C A T I O N S
Serial Control
Interface
Clock
Input
FCLKN
LCLKP
LCLKN
PLL
LVDS
LVDS
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Medical Imaging
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Wireless Infrastructure
IP1
IN1
D1N
D1P
Digital
Gain
ADC
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Test and Measurement
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Instrumentation
IP2
IN2
D2N
D2P
Digital
Gain
ADC
LVDS
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•
•
•
•
•
•
•
•
IP8
IN8
D8N
D8P
Digital
Gain
ADC
LVDS
©2009 CADEKA Microcircuits LLC
www.cadeka.com