CD74HC7046A,
CD74HCT7046A
Data sheet acquired from Harris Semiconductor
SCHS218C
Phase-Locked Loop
with VCO and Lock Detector
February 1998 - Revised October 2003
Features
Description
• Center Frequency of 18MHz (Typ) at V
Minimum Center Frequency of 12MHz at V
= 5V,
The CD74HC7046A and CD74HCT7046A high-speed
silicon-gate CMOS devices, specified in compliance with
JEDEC Standard No. 7A, are phase-locked-loop (PLL)
circuits that contain a linear voltage-controlled oscillator
(VCO), two-phase comparators (PC1, PC2), and a lock
detector. A signal input and a comparator input are common
to each comparator. The lock detector gives a HIGH level at
pin 1 (LD) when the PLL is locked. The lock detector
CC
CC = 4.5V
[ /Title
(CD74
HC704
6A,
CD74
HCT70
46A)
• Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
capacitor must be connected between pin 15 (C ) and pin
LD
8 (Gnd). For a frequency range of 100kHz to 10MHz, the
lock detector capacitor should be 1000pF to 10pF,
respectively.
• Minimal Frequency Drift
/Sub-
• Zero Voltage Offset Due to Op-Amp Buffer
ject
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input amplifiers.
With a passive low-pass filter, the 7046A forms a second-
order loop PLL. The excellent VCO linearity is achieved by
the use of linear op-amp techniques.
• Operating Power-Supply Voltage Range
(Phase-
Locked
Loop
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
TEMP. RANGE
o
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
CD74HC7046AE
( C)
PACKAGE
16 Ld PDIP
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
CD74HC7046AM
CD74HC7046AMT
CD74HC7046AM96
CD74HCT7046AE
CD74HCT7046AM
CD74HCT7046AMT
CD74HCT7046AM96
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Applications
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
• Related Literature
- AN8823, CMOS Phase-Locked-Loop Application
Using the CD74HC/HCT7046A and
CD74HC/HCT7046A
0.1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1