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CD74HC595DWE4 PDF预览

CD74HC595DWE4

更新时间: 2024-11-18 20:08:47
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
21页 756K
描述
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16

CD74HC595DWE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.4针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.13计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:10.3 mm
逻辑集成电路类型:SERIAL IN PARALLEL OUT最大频率@ Nom-Sup:25000000 Hz
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):300 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:25 MHzBase Number Matches:1

CD74HC595DWE4 数据手册

 浏览型号CD74HC595DWE4的Datasheet PDF文件第2页浏览型号CD74HC595DWE4的Datasheet PDF文件第3页浏览型号CD74HC595DWE4的Datasheet PDF文件第4页浏览型号CD74HC595DWE4的Datasheet PDF文件第5页浏览型号CD74HC595DWE4的Datasheet PDF文件第6页浏览型号CD74HC595DWE4的Datasheet PDF文件第7页 
ꢇ ꢈꢉꢊ ꢋ ꢌꢄ ꢊꢍ ꢋ ꢎꢏ ꢐ ꢊꢌ ꢋꢏ ꢎ  
SCHS353 − JANUARY 2004  
DW, E, M, NS, OR SM PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
8-Bit Serial-In, Parallel-Out Shift  
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Can Drive Up  
To 15 LSTTL Loads  
Q
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
B
Q
C
D
A
Q
SER  
OE  
Low Power Consumption, 80-µA Max I  
Typical t = 14 ns  
pd  
6-mA Output Drive at 5 V  
CC  
Q
E
Q
12 RCLK  
F
11  
10  
9
Q
SRCLK  
SRCLR  
G
Low Input Current of 1 µA Max  
Shift Register Has Direct Clear  
Q
H
GND  
Q
H  
description/ordering information  
The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage  
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and  
storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial  
output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.  
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both  
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − E  
Tube of 25  
Tube of 40  
Reel of 2000  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 80  
Reel of 2000  
CD74HC595E  
CD74HC595E  
CD74HC595DW  
CD74HC595DWR  
CD74HC595M  
SOIC − DW  
HC595M  
−55°C to 125°C  
CD74HC595M96  
CD74HC595MT  
CD74HC595NSR  
CD74HC595SM  
CD74HC595SM96  
SOIC − M  
HC595M  
SOP − NS  
HC595M  
HJ595  
SSOP − SM  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢖꢜ ꢛ ꢧꢢꢡ ꢟ ꢠ ꢡ ꢛꢙ ꢚꢛ ꢜ ꢝ ꢟ ꢛ ꢠ ꢤꢣ ꢡ ꢘꢚ ꢘꢡꢞ ꢟꢘ ꢛꢙꢠ ꢤꢣ ꢜ ꢟꢩ ꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢋꢣꢪ ꢞꢠ ꢊꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ  
ꢠ ꢟ ꢞ ꢙꢧ ꢞ ꢜꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢖꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CD74HC595DWE4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC595DWR TI

完全替代

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
CD74HC595DW TI

完全替代

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

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IC,SHIFT REGISTER,HC-CMOS,SOP,16PIN,PLASTIC