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CD74HC4059M96E4 PDF预览

CD74HC4059M96E4

更新时间： 2024-02-18 20:35:50
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
12页 208K
描述
High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

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CD74HC4059M96E4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP24,.4
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.49
其他特性：PROGRAMMABLE TO DIVIDE INPUT BY 3-15999计数方向：DOWN
系列：HC/UHJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：15.4 mm
负载/预设输入：YES逻辑集成电路类型：DIVIDE BY N COUNTER
最大频率@ Nom-Sup：18000000 Hz工作模式：SYNCHRONOUS
湿度敏感等级：1功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：300 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Prescaler/Multivibrators
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mm最小 fmax：21 MHz
Base Number Matches：1

CD74HC4059M96E4 数据手册

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CD54HC4059, CD74HC4059  
Data sheet acquired from Harris Semiconductor  
SCHS206B  
High-Speed CMOS Logic  
CMOS Programmable Divide-by-N Counter  
February 1998 - Revised May 2003  
Features  
Description  
• Synchronous Programmable ÷N Counter N = 3 to 9999  
or 15999  
The ’HC4059 are high-speed silicon-gate devices that are  
pin-compatible with the CD4059A devices of the CD4000B  
series. These devices are divide-by-N down-counters that  
can be programmed to divide an input frequency by any  
number “N” from 3 to 15,999. The output signal is a pulse  
one clock cycle wide occurring at a rate equal to the input  
frequency divide by N. The down-counter is preset by means  
of 16 jam inputs.  
[ /Title  
(CD74  
HC4059  
)
• Presettable Down-Counter  
• Fully Static Operation  
• Mode-Select Control of Initial Decade Counting  
Function (÷10, 8, 5, 4, 2)  
/Sub-  
ject  
• Master Preset Initialization  
The three Mode-Select Inputs K , K and K determine the  
a
b
c
(High-  
Speed  
CMOS  
Logic  
CMOS  
Pro-  
modulus (“divide-by” number) of the first and last counting  
sections in accordance with the truth table. Every time the first  
(fastest) counting section goes through one cycle, it reduces by  
1 the number that has been preset (jammed) into the three  
decades of the intermediate counting section an the last  
counting section, which consists of flip-flops that are not  
needed for opening the first counting section. For example, in  
the ÷2 mode, only one flip-flop is needed in the first counting  
section. Therefore the last counting section has three flip-flops  
that can be preset to a maximum count of seven with a place  
• Latchable ÷N Output  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
value of thousands. If ÷10 is desired for the first section, K is  
a
set “high”, K “high” and K “low”. Jam inputs J1, J2, J3, and J4  
b
c
• HC Types  
are used to preset the first counting section and there is no last  
counting section. The intermediate counting section consists of  
three cascaded BCD decade (÷10) counters presettable by  
means of Jam Inputs J5 through J16.  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
The Mode-Select Inputs permit frequency-synthesizer  
channel separations of 10, 12.5, 20, 25 or 50 parts. These  
inputs set the maximum value of N at 9999 (when the first  
counting section divides by 5 or 10) or 15,999 (when the first  
counting section divides by 8, 4, or 2).  
Applications  
• Communications Digital Frequency Synthesizers;  
VHF, UHF, FM, AM, etc.  
• Fixed or Programmable Frequency Division  
The three decades of the intermediate counter can be preset  
to a binary 15 instead of a binary 9, while their place values  
are still 1, 10, and 100, multiplied by the number of the ÷N  
mode. For example, in the ÷8 mode, the number from which  
counting down begins can be preset to:  
• “Time Out” Timer for Consumer-Application Industrial  
Controls  
Ordering Information  
3rd Decade  
2nd Decade  
1st Decade  
Last Counting Section  
1500  
150  
15  
TEMP. RANGE  
o
PART NUMBER  
CD54HC4059F3A  
CD74HC4059E  
( C)  
PACKAGE  
24 Ld CERDIP  
24 Ld PDIP  
-55 to 125  
-55 to 125  
-55 to 125  
1000  
The total of these numbers (2665) times 8 equals 12,320.  
The first counting section can be preset to 7. Therefore,  
21,327 is the maximum possible count in the ÷8 mode.  
CD74HC4059M96  
24 Ld SOIC  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel.  
The highest count of the various modes is shown in the  
Extended Counter Range column. Control inputs K and K  
b
c
can be used to initiate and lock the counter in the “master  
preset” state. In this condition the flip-flops in the counter are  
preset in accordance with the jam inputs and the counter  
remains in that state as long as K and K both remain low. The  
b
c
counter begins to count down from the preset state when a  
counting mode other than the master preset mode is selected.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
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CD74HC4059M96E4 替代型号

型号 品牌 替代类型 描述 数据表
CD4059AM TI

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 High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

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