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CD74HC237PWG4 PDF预览

CD74HC237PWG4

更新时间： 2024-11-21 05:18:15
品牌 Logo 应用领域
德州仪器 - TI 解复用器锁存器
页数 文件大小 规格书
19页 528K
描述
High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

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CD74HC237PWG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.31其他特性：ADDRESS LATCHES; 3 ENABLE INPUTS
系列：HC/UH输入调节：LATCHED
JESD-30 代码：R-PDSO-G16长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：OTHER DECODER/DRIVER
最大I（ol）：0.004 A功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
Prop。Delay @ Nom-Sup：48 ns传播延迟（tpd）：240 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Decoder/Drivers最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

CD74HC237PWG4 数据手册

 浏览型号CD74HC237PWG4的Datasheet PDF文件第2页浏览型号CD74HC237PWG4的Datasheet PDF文件第3页浏览型号CD74HC237PWG4的Datasheet PDF文件第4页浏览型号CD74HC237PWG4的Datasheet PDF文件第5页浏览型号CD74HC237PWG4的Datasheet PDF文件第6页浏览型号CD74HC237PWG4的Datasheet PDF文件第7页 
CD74HC137, CD74HCT137,  
CD54HC237, CD74HC237,  
Data sheet acquired from Harris Semiconductor  
SCHS146F  
CD74HCT237  
High-Speed CMOS Logic, 3- to 8-Line  
Decoder/Demultiplexer with Address Latches  
March 1998 - Revised October 2003  
Both circuits have three binary select inputs (A0, A1 and A2)  
that can be latched by an active High Latch Enable (LE)  
signal to isolate the outputs from select-input changes. A  
“Low” LE makes the output transparent to the input and the  
circuit functions as a one-of-eight decoder. Two Output  
Features  
• Select One of Eight Data Outputs  
- Active Low for CD74HC137 and CD74HCT137  
- Active High for ’HC237 and CD74HCT237  
[ /Title  
(CD74  
HC137  
,
CD74  
HCT13  
7,  
CD74  
HC237  
,
CD74  
HCT23  
7)  
Enable inputs (OE and OE ) are provided to simplify  
1
to  
0
• l/O Port or Memory Selector  
cascading  
and  
facilitate  
demultiplexing.  
The  
demultiplexing function is accomplished by using the A , A ,  
0
1
• Two Enable Inputs to Simplify Cascading  
A inputs to select the desired output and using one of the  
2
• Typical Propagation Delay of 13ns at V  
o
= 5V,  
other Output Enable inputs as the data input while holding  
the other Output Enable input in its active state. In the  
CD74HC137 and CD74HCT137 the selected output is a  
“Low”; in the ’HC237 and CD74HCT237 the selected output is  
a “High”.  
CC  
15pF, T = 25 C (CD74HC237)  
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
Ordering Information  
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC237F3A  
CD74HC137E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
/Sub-  
ject  
(High  
Speed  
• HC Types  
- 2V to 6V Operation  
CD74HC137PW  
CD74HC137PWR  
CD74HC137PWT  
CD74HC237E  
- High Noise Immunity: N = 30%, N = 30%, of V  
IL IH  
CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
CD74HC237M  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
CD74HC237MT  
CD74HC237M96  
CD74HC237NSR  
CD74HC237PW  
CD74HC237PWR  
CD74HC237PWT  
CD74HCT137E  
CD74HCT137MT  
CD74HCT137M96  
CD74HCT237E  
Description  
The  
CD74HC137,  
CD74HCT137,  
’HC237,  
and  
CD74HCT237 are high speed silicon gate CMOS decoders  
well suited to memory address decoding or data routing  
applications. Both circuits feature low power consumption  
usually associated with CMOS circuitry, yet have speeds  
comparable to low power Schottky TTL logic.  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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CD74HC237PWG4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC237PWR TI

功能相似

 High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
74AC11138PW TI

功能相似

 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

与CD74HC237PWG4相关器件

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CD74HC237PWR TI

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 		High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC237PWRE4 TI

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 		High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC237PWRE4 ROCHESTER

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 		Decoder/Driver, HC/UH Series, True Output, CMOS, PDSO16, GREEN, PLASTIC, TSSOP-16
CD74HC237PWRG4 TI

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 		High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC237PWT TI

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 		High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC237PWTE4 TI

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 		High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC237PWTE4 ROCHESTER

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 		Decoder/Driver, HC/UH Series, True Output, CMOS, PDSO16, GREEN, PLASTIC, TSSOP-16
CD74HC237PWTG4 TI

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 		High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC238 TI

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 		High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting
CD74HC238E TI

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 		High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting

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