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CD74HC238NSR96 PDF预览

CD74HC238NSR96

更新时间： 2024-09-27 23:41:19
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页数 文件大小 规格书
7页 34K
描述
DECODER/DEMUX|3-TO-8-LINE|HC-CMOS|SOP|16PIN|PLASTIC

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CD74HC238NSR96 数据手册

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CD54/74HC138, CD54/74HCT138,  
CD54/74HC238, CD54/74HCT238  
Data sheet acquired from Harris Semiconductor  
SCHS147D  
High Speed CMOS Logic 3-to-8 Line Decoder/  
Demultiplexer Inverting and Non-Inverting  
October 1997 - Revised April 2002  
Features  
Ordering Information  
• Select One Of Eight Data Outputs  
Active Low for 138, Active High for 238  
TEMP. RANGE  
o
PART NUMBER  
CD54HC138F  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
[ /Title  
(CD74  
HC138  
,
CD74  
HCT13  
8,  
CD74  
HC238  
,
CD74  
HCT23  
8)  
• l/O Port or Memory Selector  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Three Enable Inputs to Simplify Cascading  
CD54HC138F3A  
CD74HC138E  
• Typical Propagation Delay of 13ns at V  
CC  
= 5V,  
o
C = 15pF, T = 25 C  
L
A
CD74HC138M  
CD54HCT138F  
CD54HCT138F3A  
CD74HCT138E  
CD74HCT138M  
CD54HC238F3A  
CD74HC238E  
16 Ld SOIC  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
16 Ld SOIC  
16 Ld CERDIP  
16 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
/Sub-  
ject  
(High  
Speed  
- 2V to 6V Operation  
CD74HC238M  
CD74HC238NSR  
CD54HCT238F3A  
CD74HCT238E  
CD74HCT238M  
NOTES:  
16 Ld SOIC  
16 Ld SOP  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
16 Ld CERDIP  
16 Ld PDIP  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
16 Ld SOIC  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
Description  
2. Wafer and die for this part number is available which meets all  
electrical specifications. Please contact your local TI sales office  
or customer service for ordering information.  
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high  
speed silicon gate CMOS decoders well suited to memory  
address decoding or data routing applications. Both circuits  
feature low power consumption usually associated with  
CMOS circuitry, yet have speeds comparable to low power  
Schottky TTL logic. Both circuits have three binary select  
inputs (A0, A1 and A2). If the device is enabled, these inputs  
determine which one of the eight normally high outputs of  
the HC/HCT138 series will go low or which of the normally  
low outputs of the HC/HCT238 series will go high.  
Two active low and one active high enables (E1, E2, and E3)  
are provided to ease the cascading of decoders. The  
decoder’s 8 outputs can drive 10 low power Schottky TTL  
equivalent loads.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2002, Texas Instruments Incorporated  
1
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