CD74HC137, CD74HCT137,
CD54/74HC237, CD74HCT237
Data sheet acquired from Harris Semiconductor
SCHS146C
High Speed CMOS Logic, 3-to-8 Line Decoder
Demultiplexer with Address Latches
March 1998 - Revised July 2002
Features
Description
• Select One of Eight Data Outputs
The
CD74HC137,
CD74HCT137,
’HC237,
and
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.
- Active Low for CD74HC137 and CD74HCT137
- Active High for ’HC237 and CD74HCT237
[ /Title
(CD74
HC137
,
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
Both circuits have three binary select inputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE) sig-
nal to isolate the outputs from select-input changes. A “Low”
LE makes the output transparent to the input and the circuit
functions as a one-of-eight decoder. Two Output Enable
CD74
HCT13
7,
CD74
HC237
,
CD74
HCT23
7)
/Sub-
ject
• Typical Propagation Delay of 13ns at V
o
= 5V,
CC
15pF, T = 25 C (CD74HC237)
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
inputs (OE and OE ) are provided to simplify cascading
1
0
and to facilitate demultiplexing. The demultiplexing function
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
is accomplished by using the A , A , A inputs to select the
0
1
2
desired output and using one of the other Output Enable
inputs as the data input while holding the other Output
Enable input in its active state. In the CD74HC137 and
CD74HCT137 the selected output is a “Low”; in the ’HC237
and CD74HCT237 the selected output is a “High”.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
Ordering Information
(High
Speed
- High Noise Immunity: N = 30%, N = 30%, of V
IL IH
CC
at V
= 5V
TEMP. RANGE
o
CC
PART NUMBER
CD74HC137E
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
• HCT Types
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
CD74HCT137E
CD74HCT137M96
CD54HC237F
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
CD54HC237F3A
CD74HC237E
Pinout
CD54HC237
(CERDIP)
CD74HC137, CD74HCT137, CD74HCT237
(PDIP, SOIC)
CD74HC237M
CD74HC237M96
CD74HC237NSR
CD74HC237PWR
CD74HCT237E
NOTES:
CD74HC237
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
16 Ld TSSOP
16 Ld PDIP
A
A
A
1
2
3
4
5
6
7
8
16 V
15 Y
14 Y
13 Y
12 Y
11 Y
10 Y
0
1
3
CC
0
1
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
LE
2
OE
1
0
7
3
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
OE
Y
4
5
9
Y
GND
6
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2002, Texas Instruments Incorporated
1