Datasheet > CD74HC137_15

CD74HC137_15

更新时间： 2024-11-02 02:58:15

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
19页	528K
描述
High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

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数据手册

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CD74HC137_15 数据手册

CD74HC137, CD74HCT137,

CD54HC237, CD74HC237,

Data sheet acquired from Harris Semiconductor

SCHS146F

CD74HCT237

High-Speed CMOS Logic, 3- to 8-Line

Decoder/Demultiplexer with Address Latches

March 1998 - Revised October 2003

Both circuits have three binary select inputs (A0, A1 and A2)

that can be latched by an active High Latch Enable (LE)

signal to isolate the outputs from select-input changes. A

“Low” LE makes the output transparent to the input and the

circuit functions as a one-of-eight decoder. Two Output

Features

• Select One of Eight Data Outputs

- Active Low for CD74HC137 and CD74HCT137

- Active High for ’HC237 and CD74HCT237

[ /Title

(CD74

HC137

CD74

HCT13

CD74

HC237

CD74

HCT23

Enable inputs (OE and OE ) are provided to simplify

• l/O Port or Memory Selector

cascading

and

facilitate

demultiplexing.

The

demultiplexing function is accomplished by using the A , A ,

• Two Enable Inputs to Simplify Cascading

A inputs to select the desired output and using one of the

• Typical Propagation Delay of 13ns at V

= 5V,

other Output Enable inputs as the data input while holding

the other Output Enable input in its active state. In the

CD74HC137 and CD74HCT137 the selected output is a

“Low”; in the ’HC237 and CD74HCT237 the selected output is

a “High”.

15pF, T = 25 C (CD74HC237)

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

TEMP. RANGE

PART NUMBER

CD54HC237F3A

CD74HC137E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

16 Ld TSSOP

16 Ld PDIP

16 Ld SOIC

16 Ld SOP

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

/Sub-

ject

(High

Speed

• HC Types

- 2V to 6V Operation

CD74HC137PW

CD74HC137PWR

CD74HC137PWT

CD74HC237E

- High Noise Immunity: N = 30%, N = 30%, of V

IL IH

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

CD74HC237M

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

CD74HC237MT

CD74HC237M96

CD74HC237NSR

CD74HC237PW

CD74HC237PWR

CD74HC237PWT

CD74HCT137E

CD74HCT137MT

CD74HCT137M96

CD74HCT237E

Description

The

CD74HC137,

CD74HCT137,

’HC237,

and

CD74HCT237 are high speed silicon gate CMOS decoders

well suited to memory address decoding or data routing

applications. Both circuits feature low power consumption

usually associated with CMOS circuitry, yet have speeds

comparable to low power Schottky TTL logic.

16 Ld TSSOP

16 Ld PDIP

16 Ld SOIC

16 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...19

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与CD74HC137_15相关器件

型号	品牌	获取价格	描述	数据表
CD74HC137E	TI	获取价格	High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches
CD74HC137EE4	TI	获取价格	High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC137EN	ETC	获取价格	Logic IC
CD74HC137F	ETC	获取价格	Logic IC
CD74HC137H	ETC	获取价格	3-To-8-Line Demultiplexer
CD74HC137M	ROCHESTER	获取价格	HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
CD74HC137M	RENESAS	获取价格	IC,DECODER/DEMUX,3-TO-8-LINE,HC-CMOS,SOP,16PIN,PLASTIC
CD74HC137M96	RENESAS	获取价格	IC,DECODER/DEMUX,3-TO-8-LINE,HC-CMOS,SOP,16PIN,PLASTIC
CD74HC137PW	TI	获取价格	High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
CD74HC137PWE4	TI	获取价格	High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

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