CD74HC107MT

更新时间： 2024-11-15 23:00:39

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
11页	266K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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数据手册
替代型号

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CD74HC107MT 数据手册

CD54HC107, CD74HC107,

CD74HCT107

Data sheet acquired from Harris Semiconductor

SCHS139D

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

March 1998 - Revised October 2003

Features

Description

• Hysteresis on Clock Inputs for Improved Noise Immu-

nity and Increased Input Rise and Fall Times

The ’HC107 and CD74HCT107 utilize silicon gate CMOS

technology to achieve operating speeds equivalent to LSTTL

parts. They exhibit the low power consumption of standard

CMOS integrated circuits, together with the ability to drive 10

LSTTL loads.

[ /Title

(CD74

HC107

CD74

HCT10

/Sub-

ject

(Dual

J-K

Flip-

Flop

with

Reset

Nega-

tive-

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

These ﬂip-ﬂops have independent J, K, Reset and Clock

inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Reset is

accomplished asynchronously by a low level input.

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

• Fanout (Over Temperature Range)

This device is functionally identical to the HC/HCT73 but

differs in terminal assignment and in some parametric limits.

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

The HCT logic family is functionally as well as pin compatible

• Wide Operating Temperature Range . . . -55 C to 125 C with the standard LS family.

• Balanced Propagation Delay and Transition Times

Ordering Information

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

TEMP. RANGE

PART NUMBER

CD54HC107F3A

CD74HC107E

( C)

PACKAGE

14 Ld CERDIP

14 Ld PDIP

14 Ld SOIC

14 Ld PDIP

• HC Types

-55 to 125

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC107M

at V

= 5V

CD74HC107MT

CD74HC107M96

CD74HCT107E

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Pinout

CD54HC107 (CERDIP)

CD74HC107 (PDIP, SOIC)

CD74HCT107 (PDIP)

TOP VIEW

14 V

13 1R

12 1CP

11 2K

10 2R

2CP

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...11

中文翻译

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CD74HC107MT 替代型号

型号	品牌	替代类型	描述	数据表
CD74HC107MTE4	TI	类似代替	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HC107M	TI	类似代替	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HC107M96	TI	类似代替	Dual J-K Flip-Flop with Reset Negative-Edge Trigger

与CD74HC107MT相关器件

型号	品牌	获取价格	描述	数据表
CD74HC107MTE4	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HC107MTG4	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HC109	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HC109E	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HC109EE4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HC109EN	ETC	获取价格	Logic IC
CD74HC109EX	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,PLASTIC
CD74HC109F	ETC	获取价格	Logic IC
CD74HC109H	ETC	获取价格	J-K-Type Flip-Flop
CD74HC109M	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

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