CD54HC109, CD74HC109,
CD54HCT109, CD74HCT109
Data sheet acquired from Harris Semiconductor
SCHS140E
Dual J-K Flip-Flop with Set and Reset
Positive-Edge Trigger
March 1998 - Revised October 2003
Features
Description
• Asynchronous Set and Reset
• Schmitt Trigger Clock Inputs
The ’HC109 and ’HCT109 are dual J-K flip-flops with set and
reset. The flip-flop changes state with the positive transition
of Clock (1CP and 2CP).
[ /Title
(CD74H
C109,
CD74H
CT109)
/Subject
(Dual J-
K Flip-
Flop
• Typical f
MAX
= 54MHz at V = 5V, C = 15pF,
CC L
The flip-flop is set and reset by active-low S and R,
respectively. A low on both the set and reset inputs
simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously
results in an unpredictable output condition.
o
T = 25 C
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
Ordering Information
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
o
PART NUMBER
CD54HC109F3A
CD54HCT109F3A
CD74HC109E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
• Significant Power Reduction Compared to LSTTL
Logic ICs
with Set
and
Reset
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD74HC109M
at V
= 5V
CC
CD74HC109MT
CD74HC109M96
CD74HCT109E
CD74HCT109M
CD74HCT109MT
CD74HCT109M96
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinout
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CD54HC109, CD54HCT109
(CERDIP)
CD74HC109, CD74HCT109
(PDIP, SOIC)
TOP VIEW
1R
1J
1
2
3
4
5
6
7
8
16 V
CC
15 2R
14 2J
13 2K
12 2CP
11 2S
10 2Q
1K
1CP
1S
1Q
1Q
9
2Q
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1