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CD74FCT646M96 PDF预览

CD74FCT646M96

更新时间： 2024-11-06 02:58:39
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 56K
描述
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

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CD74FCT646M96 数据手册

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CD74FCT646  
Data sheet acquired from Harris Semiconductor  
SCHS261  
BiCMOS FCT Interface Logic,  
Octal Bus Transceiver/Register, Three-State  
January 1997  
Features  
Description  
The CD74FCT646 three-state octal bus transceiver/register  
uses a small geometry BiCMOS technology. The output  
stage is a combination of bipolar and CMOS transistors that  
• Buffered Inputs  
• Typical Propagation Delay: 6.8ns at V  
o
= 5V,  
CC  
T = 25 C, C = 50pF  
A
L
limits the output HIGH level to two diode drops below V  
.
CC  
• Noninverting  
This resultant lowering of output swing (0V to 3.7V)  
reduces power bus ringing (a source of EMI) and minimizes  
• SCR Latchup Resistant BiCMOS Process and  
Circuit Design  
V
bounce and ground bounce and their effects during  
CC  
• Speed of Bipolar FAST™/AS/S  
• 64mA Output Sink Current  
simultaneous output switching. The output configuration  
also enhances switching speed and is capable of sinking  
64 milliamperes.  
• Output Voltage Swing Limited to 3.7V at V  
• Controlled Output Edge Rates  
= 5V  
CC  
This device is a bus transceiver with D-Type flip-flops which  
act as internal storage registers on the LOW to HIGH transi-  
tion of either CAB or CBA clock inputs. Output Enable (OE)  
and Direction (DIR) inputs control the transceiver functions.  
Data present at the high impedance output can be stored in  
either register or both but only one of the two buses can be  
enabled as outputs at any one time. The Select controls  
(SAB and SBA) can multiplex stored and transparent (real  
time) data. The Direction control determines which data bus  
will receive data when the Output Enable (OE) is LOW. In the  
high impedance mode (Output Enable HIGH), A data can be  
stored in one register and B data can be stored in the other  
register. The clocks are not gated with the Direction (DIR)  
and Output Enable (OE) terminals; data at the A or B termi-  
nals can be clocked into the storage flip-flops at any time.  
• Input/Output Isolation to V  
CC  
• BiCMOS Technology with Low Quiescent Power  
Ordering Information  
TEMP.  
RANGE ( C)  
0 to 70  
PKG.  
NO.  
E24.3  
o
PART NUMBER  
CD74FCT646EN  
CD74FCT646M  
PACKAGE  
24 Ld PDIP  
24 Ld SOIC  
24 Ld SSOP  
0 to 70  
M24.3  
CD74FCT646SM  
0 to 70  
M24.209  
NOTE: When ordering the suffix M and SM packages, use the entire  
part number. Add the suffix 96 to obtain the variant in the tape and reel.  
Pinout  
CD74FCT646  
(PDIP, SOIC, SSOP)  
TOP VIEW  
CAB  
SAB  
DIR  
A0  
1
2
24  
23  
22  
21  
V
CC  
CBA  
SBA  
3
4
OE  
5
20 B0  
A1  
6
19  
18  
B1  
B2  
A2  
7
A3  
8
17 B3  
16 B4  
15 B5  
14 B6  
13 B7  
A4  
9
A5  
10  
11  
A6  
A7  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a trademark of Fairchild Semiconductor.  
Copyright © Harris Corporation 1997  
File Number 2393.2  
8-67  
12345678

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