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CD74FCT646SM PDF预览

CD74FCT646SM

更新时间: 2024-11-04 22:54:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
8页 56K
描述
BiCMOS FCT Interface Logic, Octal Bus Transceiver/Register, Three-State

CD74FCT646SM 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP24,.3针数:24
Reach Compliance Code:not_compliant风险等级:5.57
Is Samacsys:N其他特性:WITH DIRECTION CONTROL
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-PDSO-G24
长度:8.2 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
触发器类型:POSITIVE EDGE宽度:5.3 mm
Base Number Matches:1

CD74FCT646SM 数据手册

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CD74FCT646  
Data sheet acquired from Harris Semiconductor  
SCHS261  
BiCMOS FCT Interface Logic,  
Octal Bus Transceiver/Register, Three-State  
January 1997  
Features  
Description  
The CD74FCT646 three-state octal bus transceiver/register  
uses a small geometry BiCMOS technology. The output  
stage is a combination of bipolar and CMOS transistors that  
• Buffered Inputs  
• Typical Propagation Delay: 6.8ns at V  
o
= 5V,  
CC  
T = 25 C, C = 50pF  
A
L
limits the output HIGH level to two diode drops below V  
.
CC  
• Noninverting  
This resultant lowering of output swing (0V to 3.7V)  
reduces power bus ringing (a source of EMI) and minimizes  
• SCR Latchup Resistant BiCMOS Process and  
Circuit Design  
V
bounce and ground bounce and their effects during  
CC  
• Speed of Bipolar FAST™/AS/S  
• 64mA Output Sink Current  
simultaneous output switching. The output configuration  
also enhances switching speed and is capable of sinking  
64 milliamperes.  
• Output Voltage Swing Limited to 3.7V at V  
• Controlled Output Edge Rates  
= 5V  
CC  
This device is a bus transceiver with D-Type flip-flops which  
act as internal storage registers on the LOW to HIGH transi-  
tion of either CAB or CBA clock inputs. Output Enable (OE)  
and Direction (DIR) inputs control the transceiver functions.  
Data present at the high impedance output can be stored in  
either register or both but only one of the two buses can be  
enabled as outputs at any one time. The Select controls  
(SAB and SBA) can multiplex stored and transparent (real  
time) data. The Direction control determines which data bus  
will receive data when the Output Enable (OE) is LOW. In the  
high impedance mode (Output Enable HIGH), A data can be  
stored in one register and B data can be stored in the other  
register. The clocks are not gated with the Direction (DIR)  
and Output Enable (OE) terminals; data at the A or B termi-  
nals can be clocked into the storage flip-flops at any time.  
• Input/Output Isolation to V  
CC  
• BiCMOS Technology with Low Quiescent Power  
Ordering Information  
TEMP.  
RANGE ( C)  
0 to 70  
PKG.  
NO.  
E24.3  
o
PART NUMBER  
CD74FCT646EN  
CD74FCT646M  
PACKAGE  
24 Ld PDIP  
24 Ld SOIC  
24 Ld SSOP  
0 to 70  
M24.3  
CD74FCT646SM  
0 to 70  
M24.209  
NOTE: When ordering the suffix M and SM packages, use the entire  
part number. Add the suffix 96 to obtain the variant in the tape and reel.  
Pinout  
CD74FCT646  
(PDIP, SOIC, SSOP)  
TOP VIEW  
CAB  
SAB  
DIR  
A0  
1
2
24  
23  
22  
21  
V
CC  
CBA  
SBA  
3
4
OE  
5
20 B0  
A1  
6
19  
18  
B1  
B2  
A2  
7
A3  
8
17 B3  
16 B4  
15 B5  
14 B6  
13 B7  
A4  
9
A5  
10  
11  
A6  
A7  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a trademark of Fairchild Semiconductor.  
Copyright © Harris Corporation 1997  
File Number 2393.2  
8-67  

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