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CD74AC174M96G4 PDF预览

CD74AC174M96G4

更新时间： 2024-11-24 15:29:19
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
14页 825K
描述
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16

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CD74AC174M96G4 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65系列：AC
JESD-30 代码：R-PDSO-G16长度：9.9 mm
逻辑集成电路类型：D FLIP-FLOP位数：6
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：169 ns
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.5 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：68 MHzBase Number Matches：1

CD74AC174M96G4 数据手册

 浏览型号CD74AC174M96G4的Datasheet PDF文件第2页浏览型号CD74AC174M96G4的Datasheet PDF文件第3页浏览型号CD74AC174M96G4的Datasheet PDF文件第4页浏览型号CD74AC174M96G4的Datasheet PDF文件第5页浏览型号CD74AC174M96G4的Datasheet PDF文件第6页浏览型号CD74AC174M96G4的Datasheet PDF文件第7页 
CD74AC174  
HEX D-TYPE FLIP-FLOP  
WITH CLEAR  
SCHS346 – APRIL 2003  
E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply Voltage  
CLR  
1Q  
1
2
3
4
5
6
7
8
16  
V
CC  
Contains Six Flip-Flops With Single-Rail  
Outputs  
15 6Q  
14  
13  
12  
11  
10  
9
1D  
2D  
2Q  
3D  
3Q  
GND  
6D  
5D  
5Q  
4D  
4Q  
CLK  
Buffered Inputs  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
Balanced Propagation Delays  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
description/ordering information  
The CD74AC174 is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input and is designed for  
1.5-V to 5.5-V V operation.  
CC  
Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the  
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not  
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low  
level, the D input has no effect at the output.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
SOIC – M  
Tube  
Tube  
CD74AC174E  
CD74AC174M  
CD74AC174E  
–55°C to 125°C  
AC174M  
Tape and reel CD74AC174M96  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
D
X
H
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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